Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-06-19
2003-03-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S723000, C257S797000, C257S730000, C257S786000, C257S203000, C257S208000, C257S728000, C257S735000, C257S685000
Reexamination Certificate
active
06531782
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for die placement on a substrate generally and, more particularly, to rotating the die to minimize die-to-die routing complexity.
BACKGROUND OF THE INVENTION
Conventional multi-die semiconductor packages are organized internally about Cartesian coordinates. Dies are mounted to a substrate with the die sides aligned along an imaginary X-Y grid. Traces on the substrate carrying inter-die signals are also aligned along the imaginary X-Y grid with some corners being shortened by 45 degree routes. One consequence of the imaginary X-Y grid is that some traces on the substrate follow long and complex routes. The long and complex routes cause signal propagation delays, add to fabrication expenses, reduce reliability, and contribute to crosstalk.
A typical approach to reducing routing complexity is to align two dies so that high priority inter-die traces route between parallel facing sides of the dies. The resulting traces are short and straight thus contribute little to propagation delays and crosstalk. The parallel facing side approach is effective only when the high priority inter-die signals bonding pads are on only one side of each die. In situations where the high priority signal bonding pads are scattered across two or more die sides, then the signals of the non-facing sides must be routed over longer, more complex traces.
SUMMARY OF THE INVENTION
The present invention concerns a method of fabricating a semiconductor package that may contain two or more dies. The method generally comprises the steps of (A) mounting a first die having a first side on an assembly apparatus and (B) mounting a second die having a second side and an adjoining third side on said assembly apparatus. The second die may be oriented such that (i) the second side and the third side both face the first side and (ii) the second side and the third side are both substantially nonparallel to the first side.
The objects, features and advantages of the present invention include providing a method and architecture for mounting two dies on an assembly apparatus that may (i) reduce inter-die connection complexity, (ii) increase inter-die communication speeds, (iii) increase reliability, and/or (iv) reduce crosstalk.
REFERENCES:
patent: 4868634 (1989-09-01), Ishida et al.
patent: 5138434 (1992-08-01), Wood et al.
patent: 5189505 (1993-02-01), Bartelink
patent: 5291061 (1994-03-01), Ball
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5331235 (1994-07-01), Chun
patent: 5399898 (1995-03-01), Rostoker
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5438224 (1995-08-01), Papageorge et al.
patent: 5477082 (1995-12-01), Buckley, III et al.
patent: 5525834 (1996-06-01), Fischer et al.
patent: 5585668 (1996-12-01), Burns
patent: 5594626 (1997-01-01), Rostoker et al.
patent: 5615475 (1997-04-01), Burns
patent: 5777345 (1998-07-01), Loder et al.
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5874781 (1999-02-01), Fogal et al.
patent: 5894165 (1999-04-01), Ma et al.
patent: 5936305 (1999-08-01), Akram
patent: 5963794 (1999-10-01), Fogal et al.
patent: RE36469 (1999-12-01), Wood et al.
patent: 6048750 (2000-04-01), Hembree
patent: 6051886 (2000-04-01), Fogal et al.
patent: 6080264 (2000-06-01), Ball
patent: 6118670 (2000-09-01), Radford et al.
patent: 6127726 (2000-10-01), Bright et al.
patent: 6150724 (2000-11-01), Wenzel et al.
patent: 6160718 (2000-12-01), Vakilian
patent: 6166464 (2000-12-01), Grant
patent: 6175149 (2001-01-01), Akram
patent: 6175161 (2001-01-01), Goetz et al.
patent: 6207467 (2001-03-01), Vaiyapuri et al.
patent: 6211462 (2001-04-01), Carter, Jr. et al.
patent: 6211960 (2001-04-01), Hembree
patent: 02001102472 (2001-04-01), None
Jones Christopher W.
Wright Andrew J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Mondt Johannes P
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