Method of placing and routing for power optimization and...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Details

C716S113000, C716S124000, C716S126000, C716S130000, C716S134000, C703S019000

Reexamination Certificate

active

07992122

ABSTRACT:
A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.

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