Method of performing flip-chip underfill in a wire-bonded...

Details Method of performing flip-chip underfill in a wire-bonded... Method of performing flip-chip underfill in a wire-bonded...

2000-06-21

2002-05-21

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S112000, C438S119000, C438S124000, C438S051000, C438S612000

Reexamination Certificate

active

06391682

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to a method of performing flip-chip underfill in an integrated circuit package of the type based on a WBCOCBGA (Wire-Bonded Chip-On-Chip Ball-Grid Array) construction.
2. Description of Related Art
The WBCOCBGA package construction is a new kind of integrated circuit packaging technology that includes two semiconductor chips arranged in a chip-on-chip (COC) manner, wherein the underlying chip is electrically coupled to the substrate by means of wire bonding (WB), while the overlying chip is mounted in a flip-chip manner over the underlying chip and electrically coupled to the same by means of ball-grid array (BGA) technology. After the overlying chip is readily mounted over the underlying chip, however, a gap would be undesirably left therebetween, which, if not underfilled, would easily cause the two chips to suffer from fatigue cracking and electrical failure when the entire package structure is being subjected to high-temperature conditions. As a solution to this problem, it is an essential step in the fabrication of a WBCOCBGA-based package module to fill an underfill material, such as resin, into such a gap, so as to provide mechanical reinforcement to the two chips. The involved fabrication process is customarily referred to as flip-chip underfill.
Conventional flip-chip underfill technology, however, would easily allow the dispensed underfill material to be absorbed by nearby bonding wires and thus flashed to other parts of the package structure. This problem is illustratively depicted in the following with reference to
FIGS. 1A-1C
.
FIG. 1A
is a schematic sectional diagram of a typical WBCOCBGA-based package module. As shown, the WBCOCBGA-based package module includes a substrate
10
on which two semiconductor chips (a first semiconductor chip
21
and a second semiconductor chip
22
) are mounted in a chip-on-chip manner. The first chip
21
is mounted over the substrate
10
and electrically coupled to the same by means of a set of bonding wires
30
, while the second chip
22
is mounted by means of a plurality of solder balls
40
in a flip-chip manner over the first chip
21
. After the second chip
22
,is readily mounted over the first chip
21
, however, a gap
50
would be undesirably left therebetween due to the existence of the solder balls
40
. This gap
50
, if not underfilled, would easily cause the two chips
21
,
22
to suffer from fatigue cracking and electrical failure when the entire package structure is being subjected to high-temperature conditions.
Referring next to
FIG. 1B
, as a solution to the foregoing problem, a dispensing needle
60
is used to dispense a mass of resin
61
onto a blank side surface area
21
a
of the first chip
21
beside the second chip
22
. The dispensed resin
61
will then fill into the gap
50
through capillary action until substantially filling up the entire gap
50
.
One drawback to the forgoing underfill process, however, is that the dispensed resin
61
would easily flow wayward to the nearby bonding wires
30
and subsequently down along the sidewall of the first chip
21
to the top surface of the substrate
10
(the flashed part of the dispensed resin is indicated by the reference numeral
62
in FIG.
1
B). This would result in the waste of the dispensed resin and degradation to the quality and reliability of the finished product of the WBCOCBGA-based package module. This drawback is due to the reason that the side surface area
21
a
between the second chip
22
and the bonding wires
30
is too small in width, typically only from 200 &mgr;m to 500 &mgr;m (micrometer), and the pitch D of the bonding wires
30
, as seen from the top view of
FIG. 1C
, is typically from 60 &mgr;m to 80 &mgr;m, so that the dispensed resin
61
thereon would easily come into touch with the nearby bonding wires
30
and absorbed by the same.
Related patents include, for example, the U.S. Pat. No. 5,120,678 entitled “ELECTRICAL COMPONENT PACKAGE COMPRISING POLYMER-REINFORCED SOLDER BUMP INTERCONNECTION” and the U.S. Pat. No. 5,923,090 entitled “MICROELECTRONIC PACKAGE AND FABRICATION THEREOF”, to name just a few.
The U.S. Pat. No. 5,120,678 teaches the use of a polymer-formed dam structure to allow the dispensed underfill material to be confined within a specific area. However, this patented method is not intended for use on a WBCOCBGA-based package module. The U.S. Pat. No. 5,923,090 discloses an advanced WBCOCBGA package structure, but teaches nothing about how to prevent the dispensed underfill material from flashing to other parts of the package structure.
Therefore, there still exists a need in the semiconductor industry for an improved underfill method that can help prevent the dispensed underfill material from flashing to other parts of the package structure.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a method for performing flip-chip underfill in a WBCOCBGA-based package module, which can allow the dispensed underfill material to be confined within the target area.
It is another objective of this invention to provide a method for performing flip-chip underfill in a WBCOCBGA-based package module, which can prevent the dispensed underfill material from flashing to other parts of the package structure.
It is still another objective of this invention to provide a method for performing flip-chip underfill in a WBCOCBGA-based package module, which allows the finished product of the WBCOCBGA-based package module to be more assured in quality and reliability.
In accordance with the foregoing and other objectives, the invention proposes a new method for performing flip-chip underfill in a WBCOCBGA-based package module. The method of the invention is specifically designed for underfilling a gap under a semiconductor chip in a WBCOCBGA-based package module. The method of the invention is characterized in the steps of preserving a predetermined width of surface area beside one side of the overlying semiconductor chip in the COC configuration; and then forming a dam structure over the preserved surface area. A dispensing needle is then used to dispense an underfill material, such as resin, over the area between the dam structure and the overlying semiconductor chip. The dispensed resin can subsequently filling into the gap under the second semiconductor chip through capillary action, while being prevented from coming in touch with the bonding wires by the dam structure. Since no resin would flow to the bottomside of the underlying chip in the COC configuration, the invention allows the finished product of the WBCOCBGA-based package module to be more assured in quality and reliability than the prior art.


REFERENCES:
patent: 5120678 (1992-06-01), Moore et al.
patent: 5923090 (1999-07-01), Fallon et al.
patent: 5942798 (1999-08-01), Chiu
patent: 5981312 (1999-11-01), Farquhar et al.
patent: 6048656 (2000-04-01), Akram et al.
patent: 6153930 (2000-11-01), Hori

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