Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2002-04-18
2004-02-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S170000
Reexamination Certificate
active
06690218
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the fields of duty cycle correction and differential pair circuits, and, more specifically, to methods of performing duty cycle correction, including but not limited to methods of performing duty cycle correction using differential pair circuits.
RELATED ART
Many non-linear systems introduce into a sinusoidal signal non-linearities in the form of high frequency harmonics, each at an integer multiple of the fundamental frequency. The harmonics may be odd harmonics, i.e., harmonics the frequency of which is an odd integer multiple of the fundamental frequency, even harmonics, i.e, harmonics the frequency of which is an even integer multiple of the fundamental frequency, or both.
The introduction of even harmonics to sinusoidal signals is problematic in differential or balanced applications where it is desired to maintain odd symmetry. The reason is the non-uniform group delay, i.e., a delay which varies with frequency, typically exhibited by many transmission media delays higher frequency components of a signal more than the fundamental frequency. Because of this non-uniform group delay, transmission of the signal through the media delays the even harmonics in the sinusoidal signal more than the fundamental frequency, thus destroying the odd symmetry exhibited by the signal.
Consider, for example, a sinusoidal signal at a particular fundamental frequency. Such a signal exhibits odd symmetry only if it has a uniform (about 50%) duty cycle, i.e., a duty cycle in which the portion of the period T during which the signal is positive is about equal to the portion of the period T the signal is negative. If even harmonics are introduced into such a signal, and the signal then transmitted over a transmission media with a non-constant group delay, the duty cycle of the resultant signal will no longer be uniform, i.e., at about 50%. Consequently, the signal will no longer be suitable for differential or balanced applications where odd symmetry and a uniform duty cycle are required.
Consider, for example, the signal x
y
=1.2 sin(2&pgr;t
y
), identified with numeral
100
in FIG.
1
. The signal z
y
=sin(2t
y
)+0.2 sin(4t
y
+&pgr;/2), identified in
FIG. 1
with numeral
102
, is representative of the signal x
y
to which has been added a second order harmonic with a phase shift of &pgr;/2. In addition, the signal zz
y
=sin(2&pgr;t
y
)+0.2 sin(4&pgr;t
y
+/4), identified in
FIG. 1
with numeral
104
, is representative of the signal x
y
to which has been added a second order harmonic with a phase shift of &pgr;/4. Both the signals z
y
and zz
y
are representative of the signals that might result from introducing even harmonics into the signal x
y
, and then passing the resultant signal through a transmission medium with a non-uniform group delay. While the signal x
y
has a 50% duty cycle, it will be observed that both the signals z
y
and zz
y
have non-uniform duty cycles, i.e., signals at other that a 50% duty cycle. This can be seen most readily by comparing the zero-crossing for the signal x
y
, identified with numeral
106
, with that for the signals z
y
and zz
y
, identified with numeral
108
, and observing that the latter zero crossings occur later in time that the former zero crossing, which occurs at t
y
=0.5.
As another example, consider again the signal x
y
=1.2 sin(2t
y
), identified with numeral
100
in FIG.
2
. The signal z
y
=sin(2&pgr;t
y
)+0.2 sin(8&pgr;t
y
+&pgr;/2), identified in
FIG. 2
with numeral
202
, is representative of the signal x
y
to which has been added a fourth order harmonic with a phase shift of &pgr;/2. In addition, the signal zz
y
=sin(2&pgr;t
y
)+0.2 sin(8&pgr;t
y
+&pgr;/4), identified in
FIG. 2
with numeral
204
, is representative of the signal x
y
to which has been added a fourth order harmonic with a phase shift of &pgr;/4. Again, both the signals z
y
and zz
y
are representative of the signals that might result from introducing even harmonics into the signal x
y
, and then passing the resultant signal through a transmission medium with a non-uniform group delay. While the signal x
y
has a 50% duty cycle, it will be observed that both the signals z
y
and zz
y
have non-uniform duty cycles. This can be seen most readily by comparing the zero-crossing for the signal x
y
, identified with numeral
106
, with that for the signals z
y
and zz
y
, identified with numeral
208
, and observing that the latter zero crossings occur later in time that the former zero crossing, which occur at t
y
=0.5.
Other mechanisms exist for producing signals with non-uniform duty cycles when signals with uniform duty cycles are desired. Thus, what is needed is a method for performing duty cycle correction for signals having non-uniform duty cycles.
SUMMARY OF THE INVENTION
The invention provides a method of performing duty cycle correction of an input signal having a non-uniform duty cycle.
In this method, a signal is formed which is representative of the difference in duration between the positive and negative portions of the input signal duty cycle. A switching level is then derived from the signal. An output signal is formed through a switching action, whereby durations of positive and negative portions of the output signal duty cycle are defined by crossover points between the input signal and the switching level. The signal (and switching level) are then adjusted, if necessary, until the output signal duty cycle is substantially uniform.
In one embodiment, the signal representative of the difference in duration between the positive and negative portions of the input signal duty cycle is a DC voltage formed across one or more capacitors in a capacitor-degenerating differential pair circuit. A DC switching level is derived from the DC voltage. The output signal in this embodiment is formed through the switching actions of the differential pair circuit, whereby the durations of positive and negative portions of the output signal duty cycle are defined by crossover points between the input signal and the DC switching level. The DC voltage across the one or more capacitors (and the DC switching level) are automatically adjusted, if necessary, until the output signal duty cycle is at least substantially uniform.
REFERENCES:
patent: 5572158 (1996-11-01), Lee et al.
patent: 5907254 (1999-05-01), Chang
patent: 6107887 (2000-08-01), Zucker et al.
patent: 6169434 (2001-01-01), Portmann
patent: 6169765 (2001-01-01), Holcombe
patent: 6181178 (2001-01-01), Choi
patent: 6404281 (2002-06-01), Kobayashi
patent: 2002/0140477 (2002-10-01), Zhou et al.
patent: 0377897 (1988-12-01), None
Behzad Razavi, “A 2.5-Gb/s 15-mW Clock Recovery Circuit”, IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 472-480.
Brown Charles
Callahan Timothy P.
Kordich Donald
Nguyen Linh
Qualcomm Inc.
LandOfFree
Method of performing duty cycle correction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of performing duty cycle correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of performing duty cycle correction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3331153