Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-12-06
2009-12-15
Lam, David (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185220, C365S185240
Reexamination Certificate
active
07633813
ABSTRACT:
An erase method of a memory cell array which includes at least one block having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having a highest level by pre-programming every cell in a block selected for erase, performing an erase operation on the pre-programmed memory block, performing a soft program and a verifying operation on the memory block, dividing the memory block into a first group and a second group when the memory block is passed, performing a verifying operation on the first group and performing a soft program and a verifying operation on the first group when the first group is not passed, and performing a verifying operation on the second group when the first group is passed and performing a soft program and a verifying operation on the second group when the second group is not passed.
REFERENCES:
patent: 7050336 (2006-05-01), Tomoeda et al.
patent: 2005-085309 (2005-03-01), None
patent: 1020020036273 (2002-05-01), None
patent: 1020020048259 (2002-06-01), None
Park Se-Chun
Park Seong-Hun
Wang Jong-Hyun
Hynix / Semiconductor Inc.
Lam David
Townsend and Townsend / and Crew LLP
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