Method of partitioning, testing and diagnosing a VLSI multichip

Details Method of partitioning, testing and diagnosing a VLSI multichip Method of partitioning, testing and diagnosing a VLSI multichip

1987-06-18

1989-03-28

Smith, Jerry

Excavating

G06F 1100

Patent

active

048170933

ABSTRACT:
A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

REFERENCES:
patent: 3573751 (1971-04-01), De Lisle
patent: 4441075 (1984-04-01), McMahon
patent: 4513418 (1985-04-01), Bardell
patent: 4519078 (1985-05-01), Komonytsky

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