Method of partitioning logic designs for automatic test pattern

Details Method of partitioning logic designs for automatic test pattern Method of partitioning logic designs for automatic test pattern

1996-10-03

1999-01-19

Beausoliel, Jr., Robert W.

Excavating

371 27, 364490, G01R 3128

Patent

active

058621490

ABSTRACT:
A method used by an electronic design automation system for partitioning the logic design of an integrated circuit and generating test patterns for testing the integrated circuit. The logic design of the integrated circuit includes a gate-level description having components and nets. Nets include base nets input to the integrated circuit and apex nets output from the integrated circuit. The nets are specified by vector net notation. The method includes creating a plurality of cones of logic design from the logic design of the integrated circuit. Each cone is defined by tracing a path from an apex net, defined by a logic designer, output from a logical register of the logic design to a logic designer-defined base net affecting the logical register. A test pattern is then automatically generated for each of the traced cones of logic design. Logic cone tracing and partitioning the logic design of integrated circuits according to logical registers specified by vector net notation decreases automatic test pattern generation time in an electronic design automation system.

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P.D. Noakes, Ch. 8 "An introduction to testing and design for test techniques" from `Design & Test Techniques for VLSI & WSI Circuits,` pp. 723-743.

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