Method of partitioning a circuit

Details Method of partitioning a circuit Method of partitioning a circuit

1993-06-10

1996-04-16

Trans, Vincent N.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

055089399

ABSTRACT:
Interconnected cells, such as gates, are partitioned into blocks, such as integrated circuits, wherein the blocks have at least one constraint, such as number of pins available, on the placement of cells therein. The cells are initially assigned to blocks at random or in accordance with a previously-determined initial partition. A quality factor, such as the total number of pins on all blocks, is determined for the initial partition and cells are moved from block to block to form a new partition. The cell moves are selected so as not to violate the constraints and in accordance with the likelihood of improving the overall quality of the partition. Such partitioning is repeated and the overall quality factor is recalculated for each new partition. When the quality factor does not improve substantially from partition to partition, the last partition for which the quality factor improved is selected as the best.

REFERENCES:
patent: 5113352 (1992-05-01), Finnerty
patent: 5140526 (1992-08-01), McDermith et al.
patent: 5202840 (1993-04-01), Wong
patent: 5222031 (1993-06-01), Kaida
patent: 5229953 (1993-07-01), Isozaki et al.
patent: 5341308 (1994-08-01), Mendel
"A Linear-Time Heuristic for Improving Network Partition" by C. M. Fiduccia, R. M. Mattheyses, Proc of 19th IEEE Design Automation Conf, pp. 175-181(1982).
"An Improved Min-Cut Algorithm for Partitioning VLSI Networks" by Balakrishnan Krishnamurthy, IEEE Transactions on Computers, vol. C-33, No. 5, pp. 438-446 (1984).
"Multiply-Way Network Partitioning" by Laura A. Sanchis, IEEE Transactions on Computers, vol. 38, No. 1, pp. 62-81 (1989).

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