Method of parallelly filtering input data words to obtain...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S552000, C382S300000

Reexamination Certificate

active

07958177

ABSTRACT:
The present invention is to provide a parallel filtering method, which is implemented to an interpolation filter and comprises the steps of separating coefficients of the interpolation filter into two sets comprising the positive and negative coefficients respectively for parallelly filtering a plurality of input data pixels packed into data words inputted to the interpolation filter concurrently to obtain a first result data word, and clipping and shifting the first result data word to obtain a final output data word containing packed half-pel pixels for parallelly and efficiently filtering data stream of video without increasing the complexity, cost, size and power consumption of circuitry of an electronic video apparatus.

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Sinan Yalcin and Ilker Hamzaoglu, “A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation”, 14th IFIP International Conference on VLSI-SoC, Oct. 2006.
Wiegand, T.; Sullivan, G.J.; Bjontegaard, G.; Luthra, A.; , “Overview of the H.264/AVC video coding standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, No. 7, pp. 560-576, Jul. 2003.
C.-B. Sohn and H.-J. Cho, “An Efficient SIMD-based Quarter-Pixel Interpolation Method for H.264/AVC,” International Journal of Computer Science and Security, vol. 6, No. 11, Nov. 2006, pp. 85-89.

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