Method of parallel simulation of standard cells on a distributed

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395500, 39520001, 364488, 364489, 364490, 364491, G06F 300

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057151849

ABSTRACT:
A computer implemented method provides for simulation standard cells from an integrated circuit design in parallel on a distributed simulation system. The integrated circuit design (10) is divided into a plurality of standard cells (12-18). Characterization parameters such as temperature, process, supply voltage, edge rate and capacitive load are individually assigned (34) to each one of the standard cells. A first one (12) of the standard cells is scheduled (36) and dispatched (38) for simulation in a first computer workstation (22) on the distributed simulation system (20). A second one (14) of the standard cells is scheduled and dispatch for execution in a second computer workstation (24) on the distributed simulation system during the simulation of the first standard cell. The results of the first and second simulations are stored (40) upon completion of the respective simulation tasks.

REFERENCES:
patent: 5519848 (1996-05-01), Wloka et al.
"Development of Parallelism for Circuit Simulation by Tearing" European Design Auto Conf. IEEE 1993, pp. 12-17 (H. Onozuka et al.).
"Circuit Partitioning for Multiprocessor SPICE". IEEE Tencon 1993, pp. 1186-1189 (X. D. Jia et al.).

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