Method of optimizing the timing between signals

Details Method of optimizing the timing between signals Method of optimizing the timing between signals

2006-04-04

2006-04-04

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Timing

Reexamination Certificate

active

07024326

ABSTRACT:
A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according to which a delay test value of a clock delay line (CDL) are generated. According to the delay test values a clock signal (C) and a sample signal (S) are received through said clock delay line (CDL) and through said sample signal line (SSL), respectively. Respective phase differences for the distinct delay test values are obtained. A delay value is chosen and set for operation for which the respective obtained phase difference fits best to given target timing data.

REFERENCES:
patent: 6834255 (2004-12-01), Abrosimov et al.
patent: 2003/0236641 (2003-12-01), Liou

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