Method of optimizing signal timing delays and power consumption

Details Method of optimizing signal timing delays and power consumption Method of optimizing signal timing delays and power consumption

1985-06-06

1987-10-06

Krass, Errol A.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

046987606

ABSTRACT:
A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power-performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

REFERENCES:
patent: T935003 (1975-06-01), Linville et al.
patent: 3702003 (1972-10-01), Ramirez, Jr. et al.
patent: 4263651 (1981-04-01), Donath et al.
patent: 4593363 (1986-06-01), Burstein et al.
Donze et al., PHKO-A VLSI Design System, 19th Design Automaton Conference, IEEE, 1982, Paper 12.1, pp. 163-69.

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