Method of optimizing repeater placement in long lines of a compl

Details Method of optimizing repeater placement in long lines of a compl Method of optimizing repeater placement in long lines of a compl

1996-06-20

1998-11-17

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364491, G06F 1750

Patent

active

058385800

ABSTRACT:
A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.

REFERENCES:
patent: 4270029 (1981-05-01), Sato et al.
patent: 4317216 (1982-02-01), Kaegebein
patent: 4598399 (1986-07-01), Bath
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4826275 (1989-05-01), Heinzman
patent: 4930118 (1990-05-01), Sugihara
patent: 5097232 (1992-03-01), Stopper
patent: 5111060 (1992-05-01), Asada
patent: 5235221 (1993-08-01), Douglas et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5287289 (1994-02-01), Kageyama et al.
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5345393 (1994-09-01), Ueda
patent: 5355029 (1994-10-01), Houghton et al.
patent: 5359535 (1994-10-01), Djaja et al.
patent: 5396435 (1995-03-01), Ginetti
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5404311 (1995-04-01), Isoda
patent: 5416718 (1995-05-01), Yamazaki
patent: 5418490 (1995-05-01), Kaegebein
patent: 5426591 (1995-06-01), Ginetti et al.
patent: 5436575 (1995-07-01), Pederson et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5475605 (1995-12-01), Lin
patent: 5477474 (1995-12-01), Southgate et al.
patent: 5661661 (1997-08-01), Gregory et al.
H.-C. Tang et al., "Power dissipation models and performance improvement techniques for CMOS inverters with RC line and tree interconnections," IEEE, pp. 437-443 (Dec. 1993).
Circuits, Interconnections, and Packaging for VLSI, H.B. Bakoglu, 1990, cover, copyright, and back pages, and pp. 112-115.

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