Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Converting – per se – of an ac input to corresponding dc at an...
Patent
1996-11-06
1999-12-21
Teska, Kevin J.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Converting, per se, of an ac input to corresponding dc at an...
327292, 709204, G06F 1500
Patent
active
060060239
ABSTRACT:
Buffer trees are detected in an inputted logic circuit and sets of driver gates included in the respective buffer trees are made (in Step 102). A set of gates relating to more than one buffer tree, i.e., a group of gates to be optimized, is detected (in Step 103). The groups of gates to be optimized are classified according to the symmetry in logic structure (in Step 104). Each group of gates to be optimized is extracted (in Step 105). The buffer trees are restructured so as to be in a symmetrical relation with each other (In Step 106). Through the above process, the buffer trees are optimized to be in a symmetrical relation of logic structure. Thus, the method of optimizing the logic circuit to ensure reduction in routing area, total length of interconnections and delay of the layout after placement is accomplished.
REFERENCES:
30 .sup.th ACM/IEEE Design Automation Conference, 230-235, Hirendu Vaishnav, et al., "Routability-Driven Fanout Optimization".
Do Thuan
Mitsubishi Denki & Kabushiki Kaisha
Teska Kevin J.
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