Method of optimizing a chip pattern on a semiconductor wafer

Details Method of optimizing a chip pattern on a semiconductor wafer Method of optimizing a chip pattern on a semiconductor wafer

1996-10-10

1999-02-23

Young, Christopher G.

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

430 30, G03F 900

Patent

active

058741895

ABSTRACT:
A method is disclosed for optimizing a pattern of semiconductor chips, which includes a mask being aligned via a reference point on the mask and an alignment mark on the wafer. The relative spatial position of the alignment mark is determined by a procedure for optimizing quantities which determine the fabrication costs of a semiconductor chip, while the position of the semiconductor chips relative to each other remain fixed during the optimization.

REFERENCES:
patent: 5521036 (1996-05-01), Iwamoto et al.

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