Method of operating SAR-type ADC and an ADC using the method

Details Method of operating SAR-type ADC and an ADC using the method Method of operating SAR-type ADC and an ADC using the method

2002-06-14

2004-04-13

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S161000

Reexamination Certificate

active

06720903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of operating a successive approximation register (SAR) type analog-to-digital converter (ADC) and to an analog-to-digital converter configured to use the method.
2. Description of the Related Art
FIG. 1
shows a conventional SAR-type single-ended ADC
10
comprising an array of binary weighted capacitors, namely an array formed of N capacitors C
0
. . . C
j
. . . C
N-1
with capacitances varying according to a factor
2
j
, where j varies from 0 to N-1. An additional capacitor C
x
, with the same capacitance as the smallest capacitor (C
0
) of the array, is provided to obtain an overall array capacitance which is exactly twice the capacitance of the largest capacitor (C
N-1
) of the array. Each capacitor of the array has an electrode connected to a common node NS and another electrode connected, through a respective switch S
INj
. . . S
REFj
. . . S
GNDj
. . . , either to an input terminal 11 to receive a voltage V
IN
(referred to ground) to be converted, or to a first reference terminal to receive a first reference voltage V
REF
(referred to ground), or to a second reference terminal to receive a second reference voltage, in this example ground. The node NS is connected to the inverting input of an operational amplifier
20
, which has a non-inverting input connected to ground and operates as a comparator. The output OUT of the operational amplifier is fed back to the inverting input through a switch SW
R
. The comparator output OUT is also connected to a SAR control logic circuit
25
. The SAR control logic circuit
25
has a first output terminal at which the digital output code is produced and further output terminals that provide binary control signals B
0
. . . B
j
. . . B
N-1
, CARV
IN
and B
R
to the drivers (broadly indicated DRV) of the switches S
INj
. . . S
REFj
. . . S
GNDj
. . . and to the switch SW
R
. An analysis of the logic gates which form the switch drivers DRV shows that switches S
REFj
and S
GNDj
are equivalent to a two-way switch which is opened or closed depending on the binary value of bit Bj to connect the capacitor Cj either to V
REF
or to ground. The binary signal CARV
IN
controls switch S
INj
to open or close a connection of capacitor Cj to V
IN
and inhibits the closure of both switches S
REFj
and S
GNDj
when switch S
INj
is on.
The operation principle is that typical of an SAR-type ADC. First, signal B
R
closes switch SW
R
to connect node NS to a virtual ground and signal CARV
IN
closes switches S
IN0
. . . S
INj
. . . S
INN-1
This causes all the array capacitors to be charged to the voltage V
IN
to be converted. Then, switch SW
R
is opened, so that node NS remains floating, and the SAR control logic
25
controls, through the binary signals B
O
-B
N-1
, the switches associated with the capacitors to selectively couple each capacitor of the array to either one of the first and second voltage reference terminals (V
REF
,ground) according to the SAR technique. As a result of this operation step, node NS is brought to voltage:
V
NS
=
-
V
IN
+
∑
j
=
1
N
⁢
 
⁢
(
V
REF
2
j
)
·
b
j
where b
j
indicates the binary value of the j-th bit (associated with capacitor C
j
of the array). The operational amplifier
20
reads the sign of the voltage at node NS and outputs a corresponding digital signal. The control logic
25
is responsive to this digital signal to determine the value of the current bit of the output code and provides the capacitor array with a digital code for controlling the capacitor switches S
REFj
, S
GNDj
in the subsequent operation step. After the last step, on the SAR control logic output there is the digital code (OutputCode) corresponding to V
IN
.
A basic requirement for a correct design of a SAR-type ADC is a substantial equality of the dynamic range, i.e., the maximum swing of the voltage signal to be converted, and the Full Scale Range (FSR), i.e., the difference between the internal reference voltages (V
REF
and ground in the circuit of FIG.
1
). If an optimum performance is required, the voltage signal to be converted should not be too high so as to be cut off, which would cause a conversion saturation error, and not too much lower than the FSR, otherwise the resolution of the converter would not be used at the best.
Usually, when the signal dynamic range is known, the designer implements a reference voltage generator capable of providing an FSR at least as large as the dynamic range.
This approach brings about two problems. First, the trend to the supply voltage reduction in the integrated circuit design and the requirement of providing a proper stable biasing of the operational amplifiers which generate the voltage references limit severely the maximum obtainable FSR. Second, it is often required to handle input voltage signals having different dynamic ranges. In this case, the FSR should be adjusted to each input dynamic range if the maximum resolution is to be obtained; this solution, however, is unpractical and generally difficult, if not impossible, in its implementation. Other known solutions keep a fixed FSR and provide networks for down-scaling the input signal before it is applied to the capacitor array, as shown in
FIGS. 2 and 3
.
FIG. 2
shows an ADC
10
identical to that of
FIG. 1
with a down-scaling network
26
implemented with a simple resistor voltage divider. Four resistors R
0
, R
1
, R
2
, R
3
are shown in series between an input terminal
27
and ground. The input terminal
27
and three taps of the divider can be selectively connected to the input terminal
11
of the converter
10
through a switch SW
S
controlled by a selection register
28
. If the FSR at the input
11
of the converter
10
is known and the different dynamic ranges of the input signals are known, the divider can be easily designed to provide down-scaled replicas of the input voltage V
IN
. A code stored in the selection register
28
makes it possible to select either the non-scaled input or one of the down-scaled replicas which best fit in each case. This solution has a number of disadvantages. First of all, the divider is a load for the generator of the signal to be converted, so that, this solution cannot be used with high impedance signal generators; furthermore, when usable, it causes an additional power consumption. In this case a compromise should be taken in selecting the overall resistance of the divider, since the overall resistance should be as high as possible to reduce power consumption, but should be low enough not to limit the charging speed of the capacitor array and therefore the conversion speed. In addition, an error component due to the noise associated with the resistor arrangement adds to the input signal, thereby reducing the accuracy and linearity of the converter. Finally, the difficulty in designing resistors which provide accurate scaling of the input signal and the integrated circuit area needed for the voltage divider should be also taken into account.
To avoid that a current is drawn from the generator of the signal to be converted, a scaling arrangement
26
′, as shown in
FIG. 3
, has been proposed. In this arrangement the input signal V
IN
is applied to the non-inverting input of an operation amplifier
29
. A voltage divider comprising four resistors R
0
′, R
1
′, R
2
′, R
3
′ is connected as shown to the inverting input of the operation amplifier
29
through a switch SW
S
′ controlled by a selection register
28
′. A feed-back resistor R
F
is connected between the output and the inverting input of operation amplifier
29
. The input signal V
IN
can be down-scaled by changing the resistance between the inverting input and ground, and thus the gain of the operation amplifier, by means of a digital code stored in the selection register
28
′. This arrangement has most of the disadvantages of the arrangement shown in FIG.
2
and additional problems related with the offset, noise and pass-band of t

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