Method of operating non-volatile memory device

Details Method of operating non-volatile memory device Method of operating non-volatile memory device

2007-09-04

2007-09-04

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

C365S185330, C365S185290, C365S185280, C365S185260

Reexamination Certificate

active

11161359

ABSTRACT:
A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.

REFERENCES:
patent: 5349221 (1994-09-01), Shimoji
patent: 6011725 (2000-01-01), Eitan
patent: 6487114 (2002-11-01), Jong et al.
patent: 6862221 (2005-03-01), Melik-Martirosian et al.
Article titled “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory” offered by Yeh et al. in 2002,IEEE, pp. 931-934.
Article titled “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” offered by Eitan et al. in 2000, IEEE, pp. 543-545.

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