Method of operating non-volatile memory

Details Method of operating non-volatile memory Method of operating non-volatile memory

2005-10-11

2008-08-12

Nguyen, Dao H (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010, C365S185050, C365S185140, C365S185180, C257S311000, C257S324000, C257SE29303, C257SE29305

Reexamination Certificate

active

07411836

ABSTRACT:
A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is bigger than the fourth voltage, the third voltage is bigger than the second voltage, and the second voltage is bigger than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 7158411 (2007-01-01), Yeh et al.
patent: 2005/0056884 (2005-03-01), Osabe et al.
patent: 2007/0081393 (2007-04-01), Lue et al.
“Pines: A Novel Low Power Program/Erase, Small Ptich, 2-Bit per Cell flash Memory” By C.C. Yeh et al. / International Electron Devices Meeting, IEEE 2002 / pp. 931-936.
“Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful for EEPRM Applications” By Jan Van Houdt et al. / IEEE Transactions on Electron Devices, vol. 39, No. 5, May 1992 / pp. 1150-1156.

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