Method of operating microcomputer to minimize power dissipation

Details Method of operating microcomputer to minimize power dissipation Method of operating microcomputer to minimize power dissipation

1995-03-10

1998-04-07

Bowler, Alyssa H.

39575001, G06F 132

Patent

active

057376131

ABSTRACT:
A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a first frequency, a second memory operable at a lower second frequency, including operating the entire CMOS microcomputer at the first frequency while accessing the first memory, causing the CMOS microcomputer to dissipate power at a first level, determining from a user program currently being executed that it is necessary to access the second memory, and operating the entire CMOS microcomputer at the lower second frequency while accessing the second memory to cause the CMOS microcomputer to dissipate power at a second level which is lower than the first level. The user program is executed to set a first speed control bit to a first level indicating that the second memory is to be accessed at the second frequency, and the second frequency is selected as a system clock frequency for the entire CMOS microcomputer in response to the first level of the first speed control bit. The second frequency is selected as the system clock frequency in response to a coincidence of one of a plurality of speed control bits and a corresponding one of a plurality of chip control outputs.

REFERENCES:
patent: 5123107 (1992-06-01), Mensch, Jr.
patent: 5319771 (1994-06-01), Takeda
patent: 5450574 (1995-09-01), Madter et al.

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