Method of operating a video decoding system

Details Method of operating a video decoding system Method of operating a video decoding system

2011-08-23

2011-08-23

Rao, Andy S (Department: 2486)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240260, C348S721000

Reexamination Certificate

active

08005147

ABSTRACT:
A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

REFERENCES:
patent: 5379356 (1995-01-01), Purcell et al.
patent: 5576765 (1996-11-01), Cheney et al.
patent: 5579052 (1996-11-01), Artieri
patent: 5589885 (1996-12-01), Ooi
patent: 5598483 (1997-01-01), Purcell et al.
patent: 5646687 (1997-07-01), Botsford et al.
patent: 5774676 (1998-06-01), Stearns et al.
patent: 5815646 (1998-09-01), Purcell et al.
patent: 5818432 (1998-10-01), Tsutsumi
patent: 6538656 (2003-03-01), Cheung et al.
patent: 6630964 (2003-10-01), Burns et al.
Pirsch et al.: “VLSI Architectures for Video Compression—A Survey”, Proceedings of the IEEE, IEEE, New York, NY, USA, vol. 83 No. 2, Feb. 1, 1995, pp. 220-246, XP000501242, ISBN: 0018-9219.
U.S. Appl. No. 09/437,208 entitlted “Graphics Display System”, filed Nov. 9, 1999, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,374 entitled “Video, Audio and Graphics Decode, Composite and Display System”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,936 entitled “Video and Graphics System With an MPEG Video Decoder for Concurrent Multi-Row Decoding”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/643,223 entitled “Video and Graphics System With MPEG Specific Data Transfer Commands”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/640,670 entitled “Video and Graphics System With Video Scaling”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,930 entitled “Video and Graphics System With a Video Transport Processor”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/641,935 entitled “Video and Graphics System With Parallel Processing of Graphics Windows”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/642,510 entitled “Video and Graphics System With a Single-Port RAM”, filed Aug. 18, 2000, Inventor: Xiaodong Xie.
U.S. Appl. No. 09/642,458 entitled “Video and Graphics System With an Integrated System Bridge Controller”, Inventor: Alexander G. MacInnis et al.

Affiliated with

Also associated with

Rating

Method of operating a video decoding system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of operating a video decoding system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of operating a video decoding system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2748298