Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-01-28
2000-03-21
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518503, 36518901, 36518501, 36518514, 257324, H01L 2702
Patent
active
060409959
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Non-volatile EEPROM cells are usually employed for permanent storage of data. Various technologies have been proposed for the realization of EEPROM cells (see, for example, Lai et al., IEDM Tech. Dig. 1986, pp. 580 through 586).
On the one hand, specific MOS transistors are employed as memory cells in what are referred to as SONOS or MNOS cells. The MOS transistor comprises a gate dielectric that comprises at least a silicon nitride layer under the gate electrode and an silicon oxide layer between the silicon nitride layer and the channel region. For storing information, charge carriers are stored in the silicon nitride layer.
The thickness of the silicon oxide layer in SONOS cells amounts to a maximum of 2.2 nm. The thickness of the silicon nitride layer in modern SONOS memories usually amounts to about 10 nm. A further silicon oxide layer that comprises a thickness of 3 to 4 nm is usually provided between the silicon nitride layer and the gate electrode. These non-volatile memory cells can be electrically written and erased. In the write event, such a voltage is applied to the gate electrode that charge carriers from the substrate tunnel into the silicon nitride layer through the maximally 2.2 nm thick silicon oxide layer. For erasing, the gate electrode is wired such that the charge carriers stored in the silicon nitride layer tunnel through the maximally 2.2 nm thick silicon oxide layer into the channel region and charge carriers of the opposite conductivity type tunnel through the silicon oxide layer into the silicon nitride layer.
The SONOS cells exhibit a time of .ltoreq.10 years for the data preservation. This time is too short for many applications, for example for the storing of data in computers.
EEPROM cells with floating gate are employed as alternative to the SONOS cells. These are suitable for applications in which longer times are demanded for the data preservation. A floating gate electrode that is completely surrounded by dielectric material is arranged between a control gate electrode and the channel region of the MOS transistor in these memory cells. The information is stored on the floating gate electrode in the form of charge carriers. These memory cells, which are also referred to as FLOTOX cells, can be electrically written and erased. To that end, the control gate electrode is connected to such a potential that charge carriers flow from the channel region onto the floating gate (writing) or, respectively, charge carriers flow from the floating gate into the channel region (erasing). These FLOTOX cells exhibit times of less than 150 years for the data preservation.
Compared to the SONOS cells, however, they are complicated in structure. Further, the space requirement compared to SONOS cells is greater since the control gate electrode must laterally overlap the floating gate electrode. Finally, what is referred to as the radiation hardness of FLOTOX cells is limited. What is meant by radiation hardness is the insensitivity of the stored charge to external radiation sources and/or electromagnetic fields.
SUMMARY OF THE INVENTION
The invention is based on the problem of specifying a method for the operation of a memory cell arrangement, whereby a time of at least 150 years is achieved for the data preservation and whereby digital information stored in the memory cell arrangement can be electrically modified.
The inventive method employs a memory cell arrangement that, as memory cells, respectively comprises an MOS transistor with source zone, channel region, drain zone, gate dielectric and gate electrode that comprises a dielectric triple layer as gate dielectric. The dielectric triple layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer. The silicon nitride layer is arranged between the two silicon oxide layers. The first silicon oxide layer and the second silicon oxide layer respectively comprise a thickness of at least 3 nm.
The memory cell employed in the inventive method differs from conventional SONO
REFERENCES:
patent: 4996571 (1991-02-01), Kume et al.
patent: 5436481 (1995-07-01), Egawa et al.
patent: 5952692 (1999-09-01), Nakazato et al.
Bohm Thomas
Franosch Martin
Gruning Ulrike
Hofmann Franz
Krautschneider Wolfgang
Nguyen Viet Q.
Siemens Aktiengesellschaft
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