Method of operating a semiconductor memory circuit

Details Method of operating a semiconductor memory circuit Method of operating a semiconductor memory circuit

1982-06-30

1984-07-24

Munson, Gene M.

Static information storage and retrieval

Floating gate

Particular biasing

357 235, 357 2312, 357 41, 357 54, 357 59, G11C 1140, H01L 2978, H01L 2702, H01L 2904

Patent

active

044620900

ABSTRACT:
Disclosed is a semiconductor memory element having a semiconductor substrate of P conductivity type, source and drain regions which are of N conductivity type and formed in the substrate, a first gate insulation layer formed on the major surface of the substrate, corresponding to a channel region located between the source and drain, a floating gate electrode formed on the first gate insulation layer so as to partially overlap the channel region, a second gate insulation layer formed on the floating gate electrode, a control gate electrode formed on the second gate insulation layer so as to partially overlap the floating gate electrode, and an addressing gate electrode formed on the control gate electrode, extending to a portion of the channel region not covered by the floating gate electrode and the control gate electrode.

REFERENCES:
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3825945 (1974-07-01), Masuoka
patent: 3836992 (1974-09-01), Abbas et al.
patent: 4051464 (1977-09-01), Huang
patent: 4099196 (1978-07-01), Simko
patent: 4122544 (1978-10-01), McElroy
patent: 4258378 (1981-03-01), Wall
Das Gupta et al., "Dual-Gate FAMOS Memory Cell", IBM Technical Disclosure Bulletin, vol. 17, (1/75), p. 2266.
Iizuka et al., "Electrically Alterable Avalanche-Injection-Type MOS Read-Only Memory with Stacked-Gate Structure", IEEE Trans. Electron Devices, vol. ED-23, (4/76), pp. 379-387.

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