Method of operating a semiconductor memory array of floating...

Details Method of operating a semiconductor memory array of floating... Method of operating a semiconductor memory array of floating...

2005-04-19

2005-04-19

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S028000, C257S315000

Reexamination Certificate

active

06882572

ABSTRACT:
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench. An electrically conductive floating gate is formed over and insulated from a portion of the channel region, with a horizontally oriented edge extending therefrom. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion disposed adjacent to and insulated from the floating gate edge.

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