Method of operating a semiconductor device

Details Method of operating a semiconductor device Method of operating a semiconductor device

2000-02-01

2001-01-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185280, C257S316000, C257S321000

Reexamination Certificate

active

06172905

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to the field of semiconductor memories and more particularly to the programming of non-volatile memories to achieve a multi-state memory cell.
RELATED ART
Non-volatile memories including flash memories are well known in the field of semiconductor memory devices. In a conventional flash memory device, a single continuous floating gate structure is used for each memory cell. The single continuous floating gate structure is programmed and erased using programming and erase voltages and timings well known in the field. A conventional floating memory gate cell typically exists in one of two states representing either a logical zero or a logical one. To increase the capacity of a memory device without significantly increasing the size of the memory, it is desirable to implement a memory cell capable of representing more than two states. Non-volatile memory cells of this type, referred to throughout this disclosure as multi-state memory cells, have been historically implemented by controlling the amount of charge that is injected into the floating gate.
The reliability of multi-state memory cells is susceptible to defects in the dielectric structure between the floating gate and the substrate. More specifically, because the heavily doped continuous floating gate in a conventional memory device is conductive, a single defect in the form of a charge trap in the vicinity of the floating gate can drain all of the charge stored on the floating gate thereby undesirably erasing the corresponding memory cell. In addition, controlling the amount of injected charge can be a difficult process to control in a manufacturing environment thereby making it difficult to produce memory devices with consistently reliable programming voltages and programming times.
Moreover, conventional flash memory technologies are limited by the thickness of the tunnel oxide. Because the minimum tunnel oxide thickness cannot be effectively reduced below 5-7 nanometers without incurring significant leakage, the programming voltage required to sufficiently charge the floating gate structure must be maintained in the range of approximately 10-15 volts. To produce a programming voltage of this magnitude, it is necessary to incorporate a multi-stage charge pump and other high voltage circuitry into the design of conventional flash memory devices. The relative size of this high voltage circuitry effectively limits the scaling of the die size that can be achieved by simply scaling the size of the memory cell. Therefore, it is highly desirable to implement a non-volatile memory device with a multi-state memory cell without requiring a programming voltage significantly in excess of the operating voltage with a reliable manufacturing process.


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