Method of operating a processor at a reduced speed

Details Method of operating a processor at a reduced speed Method of operating a processor at a reduced speed

1995-09-27

1996-09-24

Heckler, Thomas M.

G06F 108

Patent

active

055600018

ABSTRACT:
An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

REFERENCES:
patent: 5175853 (1992-12-01), Kardach et al.
patent: 5276888 (1994-01-01), Kardach et al.
patent: 5291604 (1994-03-01), Kardach et al.

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