Boots – shoes – and leggings
Patent
1994-01-12
1996-05-21
Voeltz, Emanuel T.
Boots, shoes, and leggings
364490, G04F 500
Patent
active
055196438
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention is based on a method of operating a microprocessor that can be switched by a signal at one input from an inactive to an active operating state. WO 91/02303 discloses a wake-up circuit arrangement for a microprocessor which switches a microprocessor that has been switched with the aid of external signals into an inactive operating state back into an active operating state. For each input signal, a separate input circuit is required. The input circuits decouple the individual inputs from one another and ensure defined loads at each one of the inputs.
It is the object of the invention to provide a particularly easily implemented method of operating a microprocessor which can be switched from an inactive to an active operating state by a signal at one input.
SUMMARY AND ADVANTAGES OF THE INVENTION
The above object generally is achieved according to the present invention by a method of operating a microprocessor that can be switched by a signal at one input from an inactive to an active operating state, wherein after entering the inactive state, the activation signal is fed to the input after a predeterminable time.
The method according to the invention has the advantage of a particularly simple implementation and requires only a few components. The measure that, upon each transfer into the inactive state, the activation signal is given to the input after a predetermined time ensures that the microprocessor reacts properly to input signals which occur only occasionally and are processed correspondingly rarely. The transition into the inactive state, which occurs, for example, under the control of a program, reduces the residual current consumption of the microprocessor which is of particular significance for battery supplied systems.
The predeterminable time during which the microprocessor is in the inactive state must be matched to the input signals to be expected.
Advantageous features and improvements of the method according to the invention are disclosed and defined in the dependent claims.
The method according to the invention can be implemented particularly easily with a timer that receives a starting signal from the microprocessor when the latter goes into the inactive state and which, at the end of the predetermined time, sends the activation signal to the microprocessor.
According to another feature of the method according to the invention it is provided that a capacitor is charged with current by way of a terminal of the microprocessor during the active state and is discharged during the inactive state, with the activation signal being picked up at the capacitor. In these methods it must merely be ensured that the terminals of the microprocessor through which the capacitor charging and discharging current flows retain their function in the inactive state. An advantageous modification of this method provides that the capacitor is charged by way of a terminal of the microprocessor and is discharged by way of a further terminal of the microprocessor. The particular advantage of this modification is that the capacitor can be charged quickly during the active state of the microprocessor and discharged comparatively slowly during the inactive state. This measure is significant particularly if the active state is comparatively short compared to the inactive state. The predeterminable time for the inactive state may then be set to be relatively long compared to the time for the active state.
This configuration is particularly easily implemented if ohmic resistors are provided between each one of the microprocessor terminals and the capacitor, with the value of the resistance influencing the charging current being lower than the value of the resistance influencing the discharging current.
Further advantageous modifications and improvements of the method according to the invention will become evident from the further dependent claims in conjunction with the following description.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 and 2 are block circuit diagrams, each inc
REFERENCES:
patent: 4618953 (1986-10-01), Daniels et al.
patent: 4734871 (1988-03-01), Tsunoda et al.
patent: 4809280 (1989-02-01), Shonaka
patent: 4964123 (1990-10-01), Umemoto
David J. Comer--Digital Logic and State Machine Design 1984 CBS College Publishing, p. 184.
Kentrat Thomas
Pruessel Holger
Voehringer Klaus
Walter Helmut
Pesso Thomas
Robert & Bosch GmbH
Voeltz Emanuel T.
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