Method of operating a flash memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185330

Reexamination Certificate

active

11274310

ABSTRACT:
A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.

REFERENCES:
patent: 3982138 (1976-09-01), Luisi et al.
patent: 5369608 (1994-11-01), Lim et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 2001/0005015 (2001-06-01), Futatsuyama et al.
patent: 2004/0201399 (2004-10-01), Sher et al.
patent: 2004-031982 (2004-01-01), None
patent: 1020040007867 (2004-01-01), None

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