Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2001-09-12
2008-10-21
Ghayour, Mohammed (Department: 2611)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S316000
Reexamination Certificate
active
07440521
ABSTRACT:
In a normalization process, overflow occurring in limited size registers, holding the alpha or beta values in a map decoder, may be overcome by subtracting a constant value from all of the alpha or beta values when they reach a limit. Because subtracting a constant value may slow down the computation, detection of a constant value may occur on one decoding cycle and normalization on the succeeding decoding cycle. A multiplexor type circuit can be used to direct either zeros, in the normalization case, or a most significant bit(s), in computations without normalization, into the register holding the alpha or beta values. To minimize the impact on the computation by the normalization process, the multiplexor circuit can be set by the previous decoder cycle so that the computation does not have to wait for the multiplexor to be set to normalization or normal computation.
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Cameron Kelly B.
Tran Hau Thien
Broadcom Corporation
Garlick & Harrison & Markison
Ghayour Mohammed
Short Shayne X.
Torres Juan Alberto
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