Method of multiple CPU logic simulation

Details Method of multiple CPU logic simulation Method of multiple CPU logic simulation

1990-08-17

1994-01-04

Harrell, Robert B.

Boots, shoes, and leggings

3642212, 3649163, 364DIG1, 364DIG2, G06F 9455

Patent

active

052768546

ABSTRACT:
Software simulation of a multiple CPU computer system design utilizes integer type program statements having program variables typed as integer that correspond to the boolean input variables of the design equations. Each of the program variables is assigned to a digital word having at least as many bits as the number of CPUs, with the boolean value of variables for each CPU represented by one of the bits in the word as a binary one or zero. The program statements are executed on a computer and evaluated to provide a result word wherein the individual bits of the result word represent the logic output state of the boolean equation for each CPU.

REFERENCES:
patent: 4961156 (1990-10-01), Takasaki
patent: 5018089 (1991-05-01), Kanazawa

Affiliated with

Also associated with

Rating

Method of multiple CPU logic simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of multiple CPU logic simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of multiple CPU logic simulation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-315369