Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-04-10
2002-09-24
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S118000, C438S460000, C438S464000, C257S700000, C257S780000
Reexamination Certificate
active
06455355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a method of mounting an exposed-pad type of semiconductor device, a QFN (Quad Flat Non-leaded) package, over a PCB (printed circuit board) through a modified SMT (Surface Mount Technology) process, which can help prevent the problem of floated soldering of the semiconductor device over the PCB.
2. Description of Related Art
An exposed-pad type of semiconductor device is a type of integrated circuit package that is characterized by that the die pad, which is used to mount the packaged chip, is exposed to the bottom outside of the encapsulation body. One example of exposed-pad package is QFN (Quad Flat Non-leaded). During SMT process, the exposed-pad package is mounted onto a PCB in such a manner that the exposed surface of the die pad is directly soldered to the PCB's ground plane. This can help allow the packaged chip inside the encapsulation body to have a better grounding effect. A conventional SMT process for mounting an exposed-pad package over a PCB is illustratively depicted in the following with reference to
FIGS. 1A-1E
.
Referring first to FIG.
1
A and
FIG. 1B
, this conventional SMT process is utilized for mounting an exposed-pad package
10
, such as a QFN package, over a PCB
20
.
The exposed-pad package
10
includes: (i) a leadframe
11
having a die pad
12
and a plurality of electrically-conductive leads
13
; (ii) a semiconductor chip
14
mounted over the front surface
12
a of the exposed die pad
12
and electrically coupled to the electrically-conductive leads
13
by means of a plurality of bonding wires
15
, and (iii) an encapsulation body
16
for encapsulating the semiconductor chip
14
and the leadframe
11
while exposing the back surface
12
b
of the die pad
12
and the bottom surface
13
b
of the electrically-conductive leads
13
to the bottom outside thereof. The exposed-pad package
10
is so named due to the fact that its electrically-conductive leads
13
are confined within the encapsulation body
16
, rather than extending sidewards beyond the encapsulation body
16
, which can help reduce its layout area on the PCB
20
.
The PCB
20
includes a substrate
21
, a passivation layer
22
, a ground plane
23
, and a plurality of electrically-conductive fingers
24
on both sides of the ground plane
23
. The ground plane
23
is used as a mounting area for the exposed die pad
12
of the exposed-pad package
10
, and which is dimensioned to be substantially equal to the size of the exposed die pad
12
and therefore is significantly greater in area than each one of the electrically-conductive fingers
24
.
Referring further to
FIG. 1C
, in the next step, a solder material is pasted over the ground plane
23
and all the electrically-conductive fingers
24
, whereby a wide-area solder lump
31
is formed over the ground plane
23
, while a plurality of small-area solder lumps
32
are formed respectively over the electrically-conductive fingers
24
. At this stage, the wide-area solder lump
31
pasted over the ground plane
23
is substantially leveled in its topmost surface to the small-area solder lumps
32
pasted over the electrically-conductive fingers
24
.
Referring further to
FIG. 1D
, in the next step, the exposed-pad package
10
is mounted onto the PCB
20
, with the exposed die pad
12
being aligned to ground plane
23
and the outer leads
13
being aligned respectively to the electrically-conductive fingers
24
(i.e., the exposed surface of the die pad
12
is attached to the wide-area solder lump
31
, while the outer leads
13
of the exposed-pad package
10
are attached respectively to the small-area solder lumps
32
).
Next, a solder-reflow process is performed to reflow the wide-area solder lump
31
and all the small-area solder lumps
32
to thereby bond the exposed die pad
12
to the ground plane
23
and meanwhile bond the outer leads
13
respectively to the electrically-conductive fingers
24
. This completes the mounting of the exposed-pad package
10
over the PCB
20
.
Fundamentally, however, solder lumps would become centrally concentrated when melted during the solder-reflow process, resulting in expansion of the thickness thereof and thereby making the solder lumps bulged out. This reflow-incurred bulging height would increase with the area of the pasted solder lump.
Therefore, as illustrated in
FIG. 1E
, the wide-area solder lump
31
pasted over the ground plane
23
would become more expanded in thickness than the small-area solder lumps
32
pasted over the electrically-conductive fingers
24
, thus undesirably bulging out the exposed-pad package
10
to an elevated position. This problem is referred to as floated soldering.
As a consequence of the floated soldering of the exposed-pad package
10
over the ground plane
23
of the PCB
20
, the outer leads
13
of the exposed-pad package
10
would be lifted to an elevated position, thus being forced to break apart from the electrically-conductive fingers
24
(the broken part of the bonding is indicated by the reference numerals
40
in FIG.
1
E), undesirably resulting in failed or unreliable bonding between the outer leads
13
and the electrically-conductive fingers
24
. The finished circuit module constructed of the exposed-pad package
10
over the PCB
20
would be thus degraded in quality and reliability.
Related patents include, for example, the Japan Patent JP60210858A2 entitled “FLAT PACKAGE LSI”. This patent teaches the use of positional pins beneath the package body to help prevent positional shift of the mounted semiconductor device over the PCB. One drawback to this patent, however, is that the provision of the pins beneath the package body would make the fabrication of the semiconductor package more difficult to implement.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new method for mounting exposed-pad package over PCB, which can help prevent the problem of floated soldering of the exposed-pad package over the PCB.
It is another objective of this invention to provide a new method for mounting exposed-pad package over PCB, which can help securely bond the exposed-pad package in position over the PCB without having to use positional pins.
It is still another objective of this invention to provide a new method for mounting exposed-pad package over PCB, which can help assure the exposed-pad package to be more reliably bonded to the PCB.
In accordance with the foregoing and other objectives, the invention proposes a new method for mounting exposed-pad package over PCB.
By the method of the invention, a plurality of via holes are formed in the pad mounting area of the printed circuit board; and a solder material is pasted over the bottom end of each of the via holes. As the semiconductor device is mounted in position over the printed circuit board, a solder-reflow process is performed on the pasted solder material so as to cause the pasted solder material to be wetted to the entire surface of the solder-wettable layer in each of the via holes, thereby allowing the solder material to reflow to the upper end of each of the via holes where the reflowed solder is also wetted to the exposed die pad of the semiconductor device, thereby securely bonding the semiconductor device to the PCB.
Compared to the prior art, since the solder material used to bond the semiconductor device to the PCB is reflowed upwards from the bottom surface of the PCB through the via holes to the upper surface of the PCB, it allows the semiconductor device to be securely bonded in position over the PCB. The invention can therefore resolve the problem of floated soldering of exposed-pad package over PCB.
REFERENCES:
patent: 5557844 (1996-09-01), Bhatt et al.
patent: 5663529 (1997-09-01), McMillan, II et al.
patent: 5960260 (1999-09-01), Umehara et al.
patent: 6278180 (2001-08-01), Mizushima et al.
patent: 2001/0010393 (2001-08-01), Murakami
patent: 60210858 (1985-10-01), None
Chuang Jui-Yi
Lin Chieh-Yuan
Wu Chi-Chuan
Corless Peter F.
Edwards & Angell LLP
Elms Richard
Jensen Steven M.
Luu Pho M.
LandOfFree
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