Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-06-14
2004-11-23
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S712000, C257S762000, C257S717000, C438S687000, C438S653000
Reexamination Certificate
active
06822331
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention generally relates to bonding methods, such as when mounting silicon devices and packaged electronic circuit devices and packages to copper, ceramic thick film and other substrate materials, and mounting interconnect straps to silicon power devices as a replacement for conventional wire bonding. More particularly, this invention relates to a method for soldering materials having different coefficients of thermal expansion (CTE) by forming a joint structure that improves stress distribution so as to improve the thermal fatigue resistance of the joint, while also promoting and improving heat transfer through the joint and maintaining or promoting the electrical conductivity of the joint, in part by inhibiting void formation within the joint.
(2) Description of the Related Art
A variety of approaches are known for dissipating heat generated by high power semiconductor surface-mount (SM) devices. For example, heat-generating integrated circuit (IC) chips are often mounted to ceramic substrates, which have higher thermal conductivities than laminate substrates such as printed circuit boards (PCB). Alternatively or in addition, a device may be soldered to a thermal conductor or heatsink on a substrate to increase heat transfer away from the chip, yielding a structure referred to as a “thermal stack.” Because semiconductor devices (e.g., silicon), conductors (e.g., copper) and circuit boards (e.g., ceramics and laminates) have widely varying coefficients of thermal expansions (CTE), the solder joint of a thermal stack is subject to thermal fatigue if the assembly is exposed to extreme temperature cycles, as occurs in many automotive applications. The solder joint may shear or crack due to thermal fatigue, thereby reducing heat transfer from the device and leading to device overheating.
Thin solder joints with minimum voiding are required to achieve adequate heat transfer through thermal stacks used with high power semiconductors. A thin solder joint (e.g., about 0.003 inch, about 80 micrometers) is preferred because of the relatively low thermal conductivity of solders as compared to the other materials typically used in high power semiconductor thermal stacks. For example, the coefficients of thermal conductivity (k) for 60 Sn/40 Pb and 25 Sn/75 Pb solders are about 46 and 38 W/mK, respectively, as compared to copper and silicon with coefficients of about 399 and 83 W/mK, respectively. However, a thin solder joint is more susceptible to thermal fatigue if the materials it joins have widely varying CTE's, such as a silicon power IC and a copper heatsink. If a soft solder is used, a fatigue fracture is most likely to initiate at the outer periphery of the solder joint and propagate toward the center, reducing the area through which heat transfer occurs until the device eventually overheats. In contrast, if a hard solder is used in the thermal stack, a fatigue crack may originate in one of the adjacent materials. For example, in an application in which a silicon chip is soldered to copper, a fatigue crack may initiate in the silicon chip.
As noted above, minimum voiding is also required to achieve adequate heat transfer through the solder joint of a thermal stack. Solder voiding occurs in solder joints in part as a result of the capillary action that draws the surfaces being jointed together. In a thin solder joint, this capillary action can inhibit the ability for flux volatiles and gases to escape the solder joint, with the result that gas bubbles remain trapped in the solder joint. Solder joints containing many voids or a few large voids have significantly reduced heat transfer capability because the voids are barriers to heat flow. Voids can also provide a path for crack propagation through the solder joint. Large voids present at the bottom surface of a die are particularly detrimental to a silicon die.
As a solution to the above problems, solder joints of greater thicknesses have been employed to better distribute the thermally-induced stresses through the thickness of the solder joint, utilizing the ductility of the solder to buffer the CTE mismatch. While doing so has the capability of improving thermal fatigue resistance, there is a point at which the solder thickness is such that the CTE mismatch between the solder and either of the adjacent materials may become a primary source of crack initiation. This thickness is the minimum spacing desired to achieve between materials with a CTE mismatch, and will depend in part on joint area (e.g., die size) and the particular materials present in the thermal stack. In addition to the difficulty of determining this minimum solder thickness, there is the difficulty of producing a thick solder joint to a minimum thickness, such as in the range of about 0.010 to 0.025 inch (about 250 to 635 micrometers). Furthermore, and as noted above, increasing the thickness of the solder joint has the effect of increasing the thermal and electrical resistances of the circuit because of the relatively low thermal and electrical conductivity of solders. Finally, it is thought that thicker solder joints may increase the probability of voiding.
In view of the above, it would be desirable if the thermal stresses of a thermal stack could be reduced without incurring the performance and processing shortcomings associated with the use of thicker solder joints.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a joint structure and bonding method, such as when attaching an electrical circuit element to a substrate or a conductor on a substrate. The joint structure comprises a mesh infiltrated by a solder material. The mesh is preferably formed of a material having a higher thermal conductivity than the solder material. In a preferred embodiment, the mesh is formed of woven strands formed of copper or a copper alloy, such that the mesh is able to significantly improve the thermal conductivity of the joint structure beyond that possible with conventional solder materials.
In view of the above, several benefits can be realized with the present invention. One important benefit is that the mesh can be used to positively establish the thickness of the joint structure, such that the thickness of the joint structure can be tailored to improve the thermal fatigue resistance of the assembly by better distributing thermal stresses arising from a CTE mismatch between the solder and the materials of the circuit element and substrate. However, the joint structure of the present invention does not suffer from the shortcomings associated with thick solder joints of the prior art. For example, the improved fatigue resistance made possible with the greater thicknesses of the joint structure is not achieved at the expense of thermal conductivity, because the mesh fills the solder joint structure and acts as a composite material. If formed of copper or another highly thermally conductive material, the mesh is able to improve the thermal and electrical conductivity of the joint structure beyond that possible with a thin (e.g., 0.003 inch (80 micrometers)) unfilled solder joint. Furthermore, the mesh appears to further improve the resistance of the joint structure to fatigue cracking because it inhibits the creation of a thin shear plane within the joint structure. The individual columns of woven strands in the mesh are able to expand and contract independently of each other, thereby minimizing the total effect of any CTE mismatch between the mesh (e.g., copper) and the adjacent materials (e.g., silicon). Finally, the mesh provides multiple paths by which flux and other gases can escape the joint structure, such that the formation of relatively large voids in the joint structure is reduced. Any large voids (e.g., contaminants that are not able to escape) are broken up by the mesh and reduced to smaller voids that are distributed and confined to openings in the mesh,
Chmielewski Stefan V.
Delphi Technologies Inc.
Erdem Fazli
Flynn Nathan J.
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