Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-01-29
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S113000
Reexamination Certificate
active
06214645
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to semiconductor packaging, and more particularly, to a method of molding a ball grid array semiconductor package that prevents the accumulation of an electrostatic charge in the package during molding, thereby preventing damage to the components in the package caused by an electrostatic discharge.
2. Description of the Related Art
The recent trend in consumer electronics has been toward smaller, lighter products having improved capabilities and capacities, which has, in turn, resulted in a demand for semiconductor chips that are smaller, more highly integrated, and of higher capacity. Accordingly, modern semiconductor packages must have excellent electrical characteristics, high heat dissipating capabilities, and a large input/output-terminal capacity, to enable such small, highly integrated, and efficient semiconductor chips to perform as expected.
Ball grid array (BGA) semiconductor packages have been proposed and widely used as an exemplary package capable of enabling small, efficient and highly integrated semiconductor chips to meet their design goals effectively. BGA packages are easily formed on a conventional printed circuit board (PCB) and can effectively reduce the overall length of electric circuits incorporating them. BGA packages also utilize power- and/or ground-bonding areas more effectively, thus yielding excellent electric characteristics. Also, the input/output terminal density of BGA packages is greater than that of conventional quad flat packages (QFPs), which better comports with the trend toward smaller, denser packages.
FIGS. 10
a
and
10
b
are top and bottom plan views, respectively, of a conventional, strip-type multiple-package PCB
10
typically used in the manufacture of BGA semiconductor packages.
FIG. 15
is an enlarged plan view showing the area around a mold runner gate located in the upper left hand corner of each individual PCB of the multiple PCB
10
of
FIG. 10
a
. The following description of the construction of the conventional PCB is with reference to
FIGS. 10
a
,
10
b
and
15
.
As shown in the drawings, the typical PCB
10
comprises a dielectric substrate
11
made of a thermosetting resin, e.g., a bismaleimidetriazine or polyimide resin. A plurality of conductive traces
12
are formed on each side of the substrate to form a predetermined circuit pattern on each side thereof. A plurality of die, or chip, mounting plates
16
are centrally provided on the top surface of the substrate
11
for the mounting of semiconductor chips thereon. A plurality of conductive via holes
13
are formed through the substrate
11
to electrically connect the conductive traces
12
of both sides of the PCB to each other. A plurality of solder ball lands
14
are electrically connected to the conductive traces
12
on the bottom surface of the substrate
11
.
A non-conductive solder mask
15
coats both sides of the substrate
11
, except for selected areas of the conductive traces
12
, e.g., around the edge of the chip mounting plate
16
, and on the solder ball lands
14
, and serves to electrically isolate the traces
12
from each other and to protect them from harmful environmental elements.
As shown in
FIGS. 10
a
and
15
, a mold runner gate
17
, comprising a thin, conductive metal plate or plating of, e.g., gold or palladium, extends from a corner of the substrate
11
to the chip mounting plate
16
, and serves to guide melted molding compound, e.g., a resin, into the region of the chip mounting plate
16
during a package molding operation described in more detail below. The bonding strength between the material of the mold gate runner
17
and the molding resin is much lower than that between the resin and the solder mask
15
, which enables the resin to be easily de-gated from the gate
17
without damaging the conductive traces
12
after molding is complete.
The mold runner gate
17
is electrically connected to a ground ring
25
formed along the edge of the chip mounting plate
16
through a conductive ground trace
21
. The grounded elements of a semiconductor chip (not shown in
FIG. 10
a
) are electrically connected to the ground ring
25
by means of bonding wires (not shown) that extend between the chip and the ground ring. In the BGA package, ground signals applied from the semiconductor chip to the mold runner gate
17
enable precise measurement of voltage drops occurring between the chip and ground. Likewise, any voltage drops occurring in the wire bonds between the chip and the conductive traces
12
can also be checked easily and precisely. The grounded mold runner gate/ground ring arrangement therefore forms an effective common ground area for purposes of complete circuit definition within the BGA package.
As seen in
FIGS. 10
a
and
10
b
, tooling holes
18
are used in the strip-shaped PCB
10
to position and fix the PCB in a molding tool assembly. Singularizing holes
19
are used as reference points during singularization, or separation, of the individual BGA packages from the multiple-package PCB, which is typically accomplished by die cutting. The dotted square
19
′ defined by the singularizing holes
19
corresponds to the line along which the substrate is cut when the individual BGA packages are separated from the plurality of packages simultaneously fabricated on the PCB
10
.
FIG. 16
is a sectional view of the PCB
10
taken along the line IV—IV in FIG.
15
. As may be seen in
FIG. 16
, the solder mask
15
is thicker than the mold runner gate
17
, and has an opening through it to expose a portion of the upper surface of the mold runner gate. The solder mask
15
is also locally relieved to expose areas on the solder ball lands
14
formed on the conductive traces
12
on the bottom surface of the PCB
10
so that solder balls (not shown) can be attached thereto.
FIG. 11
is a sectional view through the region around a via hole
13
of the PCB
10
. As shown in the drawing, the via holes
13
are formed on respective conductive traces
12
. The interior wall of the via hole
13
is plated with a conductive metal, while the solder mask
15
overlays the top surface of the trace
12
and fills the void in the via hole
13
. A solder ball
80
is welded to the solder ball land
14
and is used as an input/output terminal of the package.
FIG. 12
is a sectional view through a tooling hole
18
, as taken along the line III—III in
FIG. 10
b
.
FIG. 12
reveals that the tooling hole
18
is, like the via hole
13
, formed through the thickness of the substrate
11
of the PCB. However, unlike the via hole
13
, the tooling hole
18
does not include a conductive layer on its interior surface that electrically connects the upper and lower surfaces of the board, nor does the solder mask
15
fill the interior void of the hole.
A conventional BGA semiconductor package
1
that incorporates a conventional PCB
10
of the type described above is shown in elevational cross-section in FIG.
18
. Typically, a plurality of such packages are simultaneously fabricated on the PCB
10
in the following manner. First, a plurality of semiconductor chips
40
are mounted, typically by means of a bonding layer (not shown), on the strip-shaped PCB
10
, one on each of the chip mounting plates
16
. Each chip
40
is then electrically connected to areas on the conductive traces
12
which are free of the solder mask
15
using a plurality of fine bonding wires
50
.
After wire bonding is complete, a plurality of resin envelopes
70
are molded onto the upper surface of the PCB
10
around each of the chips
40
and its associated bonding wires
50
to encapsulate and protect them against damaging mechanical and electrical environmental elements. After molding, a plurality of solder balls
80
, which are used as the input and output terminals of the packages
1
, are respectively welded to the solder ball lands
14
. The solder ball welding step is followed by a singularizing step in which the simultaneously formed plurality
Anam Semiconductor Inc.
Nelms David
Vu David
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