Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2001-07-19
2003-03-18
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S005000, C438S007000, C438S016000, C438S692000
Reexamination Certificate
active
06534328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of modeling and controlling the endpoint of chemical mechanical polishing operations performed on a process layer, and system for accomplishing same.
2. Description of the Related Art
In modem integrated circuit devices, millions of transistors are formed above a surface of a semiconducting substrate. To perform their intended functions, these transistors, or groups of transistors, are electrically coupled together by many levels of conductive interconnections, i.e., conductive metal lines and plugs. These conductive lines and plugs allow electrical signals to propagate throughout the integrated circuit device. As the performance of integrated circuit devices has continued to increase, copper has become the material of choice for conductive interconnections in high performance devices. This is due, at least in part, to the lower resistance of copper as compared to other metals, e.g., aluminum, commonly employed in making such conductive interconnections.
Typically, conductive interconnections, e.g., lines, comprised of copper are created by forming a patterned layer of insulating material, e.g., silicon dioxide, having openings formed therein, conformally depositing a barrier metal layer, e.g, tantalum, above the patterned layer of insulating material and in the openings in the layer, conformally depositing a relatively thin copper seed layer above the barrier metal layer, and forming a relatively thick layer of copper above the patterned layer of insulating material by known electroplating techniques. Thereafter, one or more chemical mechanical polishing (CMP) operations are performed to remove the copper material positioned above the surface of the patterned insulating layer, thereby defining a plurality of copper interconnections in the openings in the patterned layer of insulating material.
Typically, the polishing operations performed on the layer of copper is a two-step process, i.e., a first timed polishing operation wherein the bulk of the excessive copper is removed at a relatively rapid removal rate, and a second endpoint polishing process at a relatively slow removal rate. This second process is typically endpointed using an optical metrology tool that detects when the copper is substantially removed from the area under observation.
However, the above-described optical endpointing technique is not without its draw-backs. For example, the time for the second process to endpoint may vary, and such variations may occur from wafer to wafer. As a result, manufacturing efficiencies may be decreased. Moreover, such endpoint variations may be indicative of other problems in the polishing system or tool that tends to decrease productivity.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to a method of modeling and controlling the endpoint of chemical mechanical polishing operations performed on a process layer, and a system for accomplishing same. In one illustrative embodiment, the method comprises providing a first wafer having a process layer formed thereabove, determining a duration of an endpoint polishing process performed on the process layer on the first wafer, providing a second wafer having a process layer formed thereabove, and modifying at least one parameter of the endpoint polishing process to be performed on the process layer formed above the second wafer based upon a variance between the determined duration of the endpoint polishing process performed on the process layer on the first wafer and a target value for the duration of the endpoint polishing process.
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Hewett Joyce S. Oey
Pasadyn Alexander J.
Ghyka Alexander
Williams Morgan & Amerson P.C.
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