Static information storage and retrieval – Powering
Reexamination Certificate
1999-08-12
2001-09-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Powering
Reexamination Certificate
active
06285621
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of semiconductor technology. Specifically, the invention deals with minimizing the access time in semiconductor memory devices.
Semiconductor memories such as, for instance, dynamic semiconductor memories (DRAMs) are fabricated from semiconductor wafers. One wafer contains a multiplicity of identical memory chips. The dictates of production mean that the electrical parameters of these individual chips vary.
An important criterion for the power assessment and the selection of dynamic semiconductor memories among the electrical parameters is the access time. The access time is the time which elapses during a reading operation after the application of the address until the data read out are valid at the output. It is determined by the design and by a multiplicity of technological parameters (poly2 etching dimension, gateoxide, spacer TEOS, . . . )
On account of tolerances of the technological parameters and the dictates of production, the access times vary both among memory chips of an individual wafer and for memory chips of different wafers of a fabrication series. In a random selection of memory chips, the access times have a normal distribution. The proportion of memory chips whose access time lies above a specific limit can only be sold at a lower price than the faster memory chips, that is to say the memory chips which have a shorter access time.
If the technological parameters are chosen such that the proportion of fast chips increases, then the proportion of defective memory chips also increases, for example as a consequence of the punch-through effect in transistors or other production-dictated faults.
In this context, European patent application EP 0 602 355 A1 discloses a voltage generator for memories and circuits which is programmable by means of fuses. An internal voltage is increased to a desired voltage in steps using a counter and permanently set by blowing the fuses.
The relationship between the supply voltage and the access time of a semiconductor memory is disclosed in Atsumi et al., “Fast Programmable 256K Read Only Memory with On-Chip Test Circuits,” in: IEEE Transactions on Electron Devices (ED 32,2/1985, No. 2, New York, USA)
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to minimize the access time of semiconductor memories, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and to specifically minimize the access time for those semiconductor devices which, on account of technological parameter fluctuations, have a longer access time than the access time which can be achieved for the technological parameters chosen.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of minimizing access time to data of a semiconductor memory by means of a supply voltage generator for generating an internal supply voltage, which comprises the following method steps:
defining a standby current of a semiconductor memory as a parameter characterizing an access time to the semiconductor memory;
assigning a value of a boost voltage to the value of the parameter, whereby a magnitude of the boost voltage is greater than the given value of an internal supply voltage of the semiconductor memory and at which boost voltage the semiconductor memory is still functional; and
setting the internal supply voltage to the value of the boost voltage.
With the above and other objects in view there is also provided, in accordance with the invention, a related method which comprises the following method steps:
defining a threshold voltage of a field-effect transistor on a semiconductor memory as a parameter characterizing an access time to the semiconductor memory;
assigning a value of a boost voltage to the value of the parameter, whereby a magnitude of the boost voltage is greater than the given value of an internal supply voltage of the semiconductor memory and at which boost voltage the semiconductor memory is still functional; and
setting the internal supply voltage to the value of the boost voltage.
The invention has the advantage that the yield of comparatively fast memory chips is increased, when all the memory chips on a wafer are measured in their entirety and all the memory chips of a fabrication series are measured in their entirety in comparison with memories in which the method according to the invention is not used. The application of the method does not impair the yield of functional memory chips. A further advantage of the method according to the invention is that production fluctuations which affect the access time can be compensated for after production. Moreover, the technological parameters, in particular the poly2 line width, can be dimensioned such that they lie within a reliable range in which technology-related failures are avoided.
In accordance with an added feature of the invention, the value of the access time characterizing parameter is determined after applying an external supply voltage to the semiconductor memory, as soon as the semiconductor memory has reached a state of functional readiness.
In accordance with an additional feature of the invention, the value of the access time characterizing parameter is determined during a functional test of the semiconductor memory.
In accordance with another feature of the invention, the assigning step comprises assigning the value of the boost voltage to the value of the parameter by means of experimentally determined measurement curves.
In accordance with a further feature of the invention, the setting step comprises setting the internal supply voltage to the value of the boost voltage by blowing at least one fuse of the supply voltage generator of the semiconductor memory.
In a preferred embodiment, the blowing of fuse is effected temporally in parallel with a blowing of any other fuses of the semiconductor memory.
In accordance with again an added feature of the invention, the setting step comprises controlling the supply voltage generator by means of a control circuit, whereby the threshold voltage of the field-effect transistor is transferred to the control circuit.
In accordance with a concomitant feature of the invention, the setting step comprises setting the internal supply voltage to the value of the boost voltage in steps. The preferred step of the increase is thereby 0.3 V.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for minimizing the access time in semiconductor memories, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
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“Back-bias testing in DRAMs”, Praveen Gupta, 8029 Electronic Engineering, Nov. 1985, No. 707, London, Great Britain, pp. 185-193.
Proceedings of the 1stEuropean Test Conference, Paris, Apr. 12-14, 1989, IEEE Computer Society Order No. 1937, pp. 276-283.
“Fast Programmable 256K Read Only Memory with On-Chip Test Circuits”, Shigeru Atsumi et al., 8093 IEEE Transactions on Electron Devices, Feb. 1985, No. 2, New York, pp. 503-507.
IBM Technical Disclosure Bulletin, vol. 28, No. 9, Feb. 1986, pp. 3961-3962.
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phan Trong
Stemer Werner H.
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