Method of memory reconfiguration for fault tolerant memory

Details Method of memory reconfiguration for fault tolerant memory Method of memory reconfiguration for fault tolerant memory

1982-06-01

1984-11-27

Atkinson, Charles E.

Excavating

365200, 371 11, G06F 1100, G11C 1300

Patent

active

044854714

ABSTRACT:
Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable errors is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The data is used in maintaining a list of preferred word address locations for bad bits. These preferred word locations are word addresses which contain less than a threshold level of faulty bit positions. As each faulty bit is permuted into one of these preferred word addresses, the list is updated to account for the new location of the permuted bit. Before being permuted, the actual physical memory address of a fault is used in making up the list. After permutation, the logical address of the faulty bit is used in changing the list. The process can involve categorizing of failures in accordance with type and performing algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring the memory.

REFERENCES:
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patent: 3781826 (1973-12-01), Beausoleil
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patent: 3897626 (1975-08-01), Beausoleil
patent: 4074236 (1978-02-01), Ishida
Singh et al., Word Line, Bit Line Address Interchanging to Enhance Memory Fault Tolerance, IBM Technical Disclosure Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2747-2748.
Ryan, Fault Realignment Through Grouping of Compatible Fault Memory Chips, IBM Tech. Discl. Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2753-2754.

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