Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-10-15
2003-09-30
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S675000, C438S745000, C438S756000
Reexamination Certificate
active
06627513
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of measuring polysilicon resistance, and more particularly to a method of measuring polysilicon resistance in a deep trench.
2. Description of the Prior Art
Presently, dynamic random access memory (DRAM) is widely used. The capacitor in DRAM includes two electrode plates and an insulating material therebetween. The charge storage ability of the capacitor is determined by the thickness of insulating material, the surface area of electrode plates, and electrical properties of insulating material. With the demand for highly integrated circuits and decreased critical dimension, the surface area of memory cell must be decreased, such that a large amount of memory cells can be accommodated in integrated circuits. However, the electrode plate of capacitor must has sufficient surface area to store sufficient charge. Therefore, deep trench type capacitors, which have larger surface area, have been extensively used in DRAM.
FIG. 1
shows a cross-section of a conventional trench capacitor. A pad structure
12
is formed on a silicon substrate
10
. A trench
18
is formed in the substrate
10
, and a collar oxide
20
is formed on the inner walls of the trench
18
. A first polysilicon layer
22
(6 &mgr;m), a second polysilicon layer
24
(1 &mgr;m), and a third polysilicon layer
26
(1500 Å) are in the trench
18
. The trench capacitor further includes an inner electrode
28
and a capacitor dielectric layer
30
.
Conventionally, the polysilicon resistance is measured by directly measuring polysilicon on a wafer using the four point probe method. However, the resistance of polysilicon in a deep trench cannot be known. Also, the relationship between the polysilicon resistance in the deep trench and the doping dosage cannot be known. The polysilicon resistance in the deep trench affects the refresh speed of capacitor, which in turn affects the device efficiency. Therefore, there is a need to develop a method for measuring the polysilicon resistance in a deep trench.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of measuring resistance in a deep trench using the presently used deep trench short loop. The inventive measurement method measures the resistance of polysilicon plug in a deep trench and resistance of polysilicon pad.
To achieve the above-mentioned object, the method of measuring resistance in a deep trench includes the following steps. A first substrate having a first pad structure and a first trench with a first depth is provided. A first collar insulating layer is formed on the sidewall of the first trench. A first polysilicon layer is formed in the first trench and on the first substrate, wherein the first polysilicon layer includes a first polysilicon pad on the first pad structure and a first polysilicon plug in the first trench. The first polysilicon layer and the first substrate are doped with impurity ions. A first N well is formed in the first substrate by doping with impurity ions. A second substrate having a second pad structure and a second trench with a second depth is provided, wherein the second depth is not equal to the first depth. A second collar insulating layer is formed on the sidewall of the second trench. A second polysilicon layer is formed in the second trench and on the second substrate, wherein the second polysilicon layer includes a second polysilicon pad on the second pad structure and a second polysilicon plug in the second trench. The second polysilicon layer and the second substrate are doped with impurity ions. A second N well is formed in the second substrate by doping with impurity ions. A voltage is applied to the first and second substrates respectively to obtain a first total resistance of the first substrate and a second total resistance of the second substrate. Finally, the first total resistance and second total resistance are converted by calculation to obtain a resistance of the first polysilicon plug and a resistance of the second polysilicon plug.
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Chen Liang-Hsin
Tsai Tzu-Chin
Lebentritt Michael S.
Merchant & Gould P.C.
NanyaTechnology Corporation
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