Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
2005-04-19
2005-04-19
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C713S500000, C714S047300
Reexamination Certificate
active
06882968
ABSTRACT:
A method which simulates the operating speed of an emulated target system with a consistent rate of instruction execution on a plurality of host systems with varied and variable instruction execution speeds. An arbitrary “time quantum” is selected as a referent and is multiplied by the target's speed of instruction cycle execution to determine the quantity of instructions the target system executes in the specified time period. When non-native code is executed on the host system, a counter is used to track the number of instructions executed and to interrupt when that target quantity is reached. A processor-activity-independent timing source is queried to determine the time elapsed; that measurement is then compared to the original “time quantum.” The resulting ratio is a timing reference that is independent of the operating speed characteristics of any particular host system. This reference is used to predict the operational speed of the host system and to adjust factors in the host computer and emulation process to more accurately match the target system before executing the next block of instructions and repeating the process. In certain embodiments, the time quantum is dynamically adjusted to avoid sampling frequencies, which may conflict or resonate with timing frequencies of other system activities or to place a greater or lesser load on the host system. This process results in more consistent, accurate simulation of the target system's speed on a variety of host system configurations, within the limitations and flexibility of the host environment.
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Lerner David Littenberg Krumholz & Mentlik LLP
Sony Computer Entertainment Inc.
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