Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2003-07-16
2004-10-19
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C356S237200, C257S048000
Reexamination Certificate
active
06806105
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to processing wafers, and in particular to measuring parameters indicative of the quality of the wafer processing.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (CMP) is a well-known process in the semiconductor industry used to remove and planarize layers of material deposited on a semiconductor device to achieve a planar topography on the surface of the semiconductor device. To remove and planarize the layers of the deposited material, including dielectric and metal materials, CMP typically involves wetting a pad with a chemical slurry containing abrasive components and mechanically polishing the front surface of the semiconductor device against the wetted pad to remove the layers of deposited materials on the front surface of the semiconductor device and planarize the surface.
FIG. 1
is a schematic view of a prior art CMP apparatus
10
. CMP apparatus
10
includes a wafer carrier
11
for holding a semiconductor wafer
12
having a surface
12
S to be polished. Wafer carrier
11
is mounted for continuous rotation about an axis A
1
in a direction indicated by arrow
13
via a drive motor
14
operatively connected to the wafer carrier. Wafer carrier
11
is adapted so that a force indicated by arrow
15
is exerted on semiconductor wafer
12
.
CMP apparatus
10
also includes a polishing platen
16
mounted for continuous rotation about an axis A
2
in a direction indicated by arrow
17
by a drive motor
18
operatively connected to the polishing platen. A polishing pad
19
, formed of a material such as blown polyurethane, is mounted to polishing platen
16
. A polishing slurry containing an abrasive fluid, such as silica or alumina abrasive particles suspended in either a basic or an acidic solution, is dispensed onto polishing pad
19
through a conduit
20
arranged adjacent the polishing pad, from temperature controlled reservoir
21
.
Wafer carrier
11
rotates in a direction indicated by arrow
13
about axis A
1
. Polishing platen
16
rotates in a direction indicated by arrow
17
about axis A
2
. The polishing slurry is dispensed onto polishing pad
19
through conduit
20
, from temperature controlled reservoir
21
as the wafer carrier and polishing platen rotate about their respective axes. The force between the polishing platen and the wafer carrier and their relative rotation, in combination with the mechanical abrasion and chemical effects of the slurry, serve to polish wafer surface
12
S.
FIG. 2
illustrates a semiconductor device prior to CMP. As shown, substrate
12
has a source region
112
and a drain region
114
, and also includes lightly doped drains
116
and
118
. Source and drain regions
112
and
114
are formed according to conventional processes, after formation of a gate oxide layer
122
and gate
124
. Following formation of gate
124
, a first inter-level dielectric (ILD) layer
120
is deposited over gate
124
. First ILD layer is
120
formed of silicon dioxide, but may be formed of other dielectric materials.
After formation of first ILD layer
120
, the layer is etched to form an opening that is filled with tungsten to form a contact plug
126
, which provides ohmic contact to source region
112
. Although not shown in the plane of the cross-section of
FIG. 2
, a similar contact plug is formed for drain region
114
.
Thereafter, a first metal layer
128
is deposited on first ILD layer
120
. First metal layer
128
is formed of a metal, such as copper, aluminum, or tungsten. A second ILD layer
130
, an etch stop layer (not shown), and a third ILD layer
134
are then consecutively formed on the first metal layer
128
. Layer
130
, the etch stop layer and layer
134
are formed, patterned and etched according to conventional techniques to form openings, particularly via holes
136
a
and trenches
138
a
, via holes
136
a
being contiguous with respective trenches
138
a
. That is, each via hole shares a common, upper boundary at the interface between the via hole and the trench, where the via opens into the trench. According to the structure shown, a dual-inlaid process is used to deposit a second metal layer
139
simultaneously within via holes
136
a
and trenches
138
a
to form vias
136
and interconnects
138
(i.e., lines). The third ILD layer
134
includes fine pitch dielectric portions
134
a
separating interconnects
138
from each other. Second metal layer
139
may be copper, aluminum or tungsten. In each case, the metal is put down in layer form on the order of 3,000 to 11,000 angstroms in thickness.
Once the basic structure of
FIG. 2
is in place, CMP is carried out using CMP apparatus
10
of
FIG. 1
to remove that portion of metal layer
139
above trenches
138
a
such that the trenches
138
a
form separate interconnects
138
, and the exposed surface of the semiconductor device is polished and planarized for subsequent deposition steps, such as higher-level metal interconnects. With reference now to
FIG. 3A
, it is preferred that metal layer
139
be removed by polishing such that dielectric portions
134
a
separate trenches
138
, with upper surface
12
S being planarized.
With reference now to
FIG. 3B
, it often occurs that some of the metal layer
139
is not entirely removed, leaving a “residue”
150
of material (here, a portion of metal layer
139
). Generally, residue is any material that is supposed to have been removed from the surface of the wafer during processing. Residue generally occurs in a region that has not been polished sufficiently. Residue
150
a
lies over the narrow dielectric spaces of the structure, and residue
150
b
lies over the dielectric field.
The presence of residue
150
is problematic because it is not part of the planned semiconductor structure and thus will, in all likelihood, interfere with the performance of the resulting device. For example, in
FIG. 3B
, residue
150
short-circuits interconnects
138
. Thus, the wafer shown in
FIG. 3B
would need to be re-polished, re-processed, or scrapped, unless the amount of residue was deemed minimal enough to allow the wafer to continue on to the next process.
Unfortunately, the most effective method presently available for determining if residue is present on a wafer appears to be visual inspection of the wafer surface after it has been polished. This is a time-consuming and labor-intensive process. Accordingly, it would be preferred to have an automated, time-saving way to assess the presence or absence of residue.
One approach to measuring residue is to treat the thin layer of typically metalic residue as a transparent film, and to measure its thickness as part of an homogenous film stack with an instrument like the KLA/Tencor UV1050, available from KLA/Tencor, Inc. This method is suitable for measuring residue
150
b
overlying a large area of field dielectric, but has a general requirement that constrains its utility. The region where the residue measurement is made must be laterally homogeneous, i.e., the stack must include only flat layers that are substantially uniform over the dimensions of the spot size of the instrument, down to the first opaque layer below the residue. This is a serious limitation since the process in question may leave residue over structures that are laterally heterogeneous over the spot size of the instrument.
For example, with reference to
FIG. 4
, residue
150
a
is in the vicinity of interconnects
138
, which, in a modern integrated circuit, can have dimensions of 250 nm or less, whereas optical instruments typically have a measurement spot-size of several microns or tens of microns. Since these features are smaller than the wavelength of light, it is not possible to focus between the features, making this method unsuitable for measuring such residue.
With reference now to
FIG. 5
, it often occurs that some regions polish faster than others causing erosion
160
and dishing
162
. In the example shown, the polish process was designed to remove metal
139
(FIG.
2
), and so removes dielectric
134
more slowly. As
Johnson Kenneth C.
Stanke Fred E.
Stallman & Pollock LLP
Therma-Wave, Inc.
Thompson Craig A.
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