Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1997-12-08
1999-12-07
Ballato, Josie
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324658, G01R 3126, G01R 2726
Patent
active
059990104
ABSTRACT:
A method for measuring the coupling capacitance between two interconnect lines of an integrated circuit structure having a ground plane. The steps include shorting the first and second lines together and measuring a first capacitance (Ct) between the ground plane and the shorted first and second lines; eliminating the short between the first and second lines; shorting the first line to the ground plane and measuring a second capacitance (C1) between the second line and the shorted ground plane and first line; eliminating the short between the first line and the ground plane; shorting the second line to the ground plane and measuring a third capacitance (Cc) between the first line and the shorted ground plane and second line; and determining the coupling capacitance between the first line and the second line according to the formula Cc=(C1+C2-Ct)/2.
REFERENCES:
patent: 4439727 (1984-03-01), Boyle
patent: 4636714 (1987-01-01), Allen
patent: 4638341 (1987-01-01), Baier et al.
patent: 4831325 (1989-05-01), Watson, Jr.
patent: 5212454 (1993-05-01), Proebsting
patent: 5305257 (1994-04-01), Aizaki
patent: 5446674 (1995-08-01), Ikeda et al.
patent: 5466956 (1995-11-01), Aeba
patent: 5519327 (1996-05-01), Consiglio
patent: 5594353 (1997-01-01), Hemphill
"Efficient Extraction of Metal Parasitic Capacitances", by G.J. Gaston and I.G. Daniels, Proc. IEEE 1995 Int. Conference on Microelectronic Test Structures, vol. 8, Mar. 1995, pp. 157-160.
"Measurement and Characterization of Multi-Layered Interconnect Capacitance for Deep Submicron VLSI Technology", by Dae-Hung Cho, et al., Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, vol. 10, Mar. 1997, pp. 91-94.
"Investigation of Interconnect Capaitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and 3-D Simulation", by Dennis Sylvester, et al., Proc. IEEE 1997 Custom Integrated Circuits Conference, pp. 491-494. (Month Unavailable).
"An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution", by James C. Chen, et al., Proc.. IEEE 1997 Int. Conference on Microelectronic Test Structures, vol. 10, Mar. 1997, pp. 77-80.
"Use of Test Structures for Characterization and Modeling of Inter-and Intra-Layer Capacitances in a CMOS Process", by Pascal Nouet., IEEE Transactions on Semiconductor Manufacturing, vol. 10, No. 2, May 1997, pp. 1-9.
"On-Chip Capacitance Measurement Circuits in VSLI Structures", by Hiroshi Iwai, IEEE Transactions on Electron Devices, vol. ED-29, No. 10, Oct. 1982, pp. 1622-1626.
"VLSI Parasitic Capacitance Determination by Flux Tubes", by W. H. Dierking and J. D. Bastian, IEEE Mar. 1982, pp. 11-18.
"Capacitance Calculations in MOSFET VLSI", by M. I. Elmasry, IEEE Electron Device Letters, vol. EDL-3, No. 1, Jan. 1982.
Arora Narain D.
Wang Jian
Ballato Josie
Fowler, II Russell E.
Kobert Russell M.
Overhauser Paul B.
Simplex Solutions, Inc.
LandOfFree
Method of measuring interconnect coupling capacitance in an IC c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of measuring interconnect coupling capacitance in an IC c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of measuring interconnect coupling capacitance in an IC c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-828365