Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1999-09-22
2000-05-16
Dutton, Brian
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
H01L 2166, G01R 3126
Patent
active
060636416
ABSTRACT:
A plurality of semiconductor circuits provided on a semiconductor wafer are arranged in a plurality of rows. The plurality of semiconductor circuits of each row are connected in series through first and second conductive layers provided between adjacent two of the semiconductor circuits of each row. The plurality of semiconductor circuits are connected to power supply terminals provided on the semiconductor wafer. The first and second conductive layers may be provided separately from the higher and lower voltage side power supply lines, or one of the first and second conductive layers may be common to one of the higher and lower voltage side power supply lines. The power supply is connected to the power supply terminals and the plurality of semiconductor circuits is aged. After the aging, the power supply is disconnected from the power supply terminals. In this state, electrical characteristics of each semiconductor circuit is measured in a state in which the semiconductor circuits is isolated from the other semiconductor circuits.
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Dutton Brian
Honda Giken Kabushiki Kaisha
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