Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-10-07
2002-04-09
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S617000, C324S1540PB
Reexamination Certificate
active
06369601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of measuring a propagation delay time of a transmission path to be connected to a semiconductor integrated circuit under test in a semiconductor integrated circuit testing apparatus and to a semiconductor integrated circuit testing apparatus using this method. More particularly, the present invention relates to a propagation delay time measuring method which is capable of measuring, in a short time duration and with high accuracy, a propagation delay time of a transmission path or line for a test pattern signal and a propagation delay time of a transmission path or line for a response signal, both the transmission paths being connected to a semiconductor integrated circuit which operates at high speed or rate and has its input terminal and its output terminal used in common, and relates to a semiconductor integrated circuit testing apparatus which is capable of accurately testing a semiconductor integrated circuit of this type using the aforesaid method.
2. Description of the Related Art
As is well known, in this technical field, a semiconductor integrated circuit (hereinafter referred to as IC) is called a logic IC in which a logical circuit portion (logic portion) is dominant or a memory IC in which a memory portion is dominant. In addition, an IC in which a logic portion and a memory portion are present in mixture on one chip is called a systematic LSI (Systematic Large Scale Integrated Circuit) or the like.
FIG. 3
shows a general configuration of a semiconductor integrated circuit testing apparatus (hereinafter referred to as IC testing apparatus) which has conventionally been used for testing and measuring these ICs. This IC testing apparatus TES comprises, roughly speaking, a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logical comparator
11
5
, a group of drivers (hereinafter referred to as a driver group)
116
, a group of analog level comparators (hereinafter referred to as a comparator group)
117
, a failure analysis memory
118
, a failure relief processor
118
A, a response time measuring device
120
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
, and a device power supply
123
.
The main controller
111
is generally constituted by a computer system, has a test program PM created by a user (programmer) and previously stored therein, and controls the entire IC testing apparatus in accordance with the test program PM. The main controller
111
is connected, via a tester bus BUS, to the pattern generator
112
, the timing generator
113
, the failure analysis memory
118
, the failure relief processor
118
A, the response time measuring device
120
, the logical amplitude reference voltage source
121
, the comparison reference voltage source
122
, the device power supply
123
, and the like.
An IC to be tested (IC under test: DUT)
119
is mounted on a test head (not shown) constructed separately from the IC testing apparatus proper. Usually, on the top portion of the test head is mounted a member called a “performance board”, and a predetermined number of IC sockets are mounted on the performance board. Consequently, the IC under test
119
is mounted on an associated one of these IC sockets. In addition, a printed board called “pin card” in this technical field is accommodated in the test head. Usually, circuits including a driver from the driver group
116
and a comparator from the comparator group
117
of the IC testing apparatus TES are formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and handling apparatus called “handler” in this technical field, and is electrically connected to the IC testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
Further, the pin cards on which circuits including the driver from driver group
116
and the comparator from comparator group
117
of the IC testing apparatus TES and the like are formed is also called “pin electronics part” in this technical field. This pin electronics part is comprised of many pin electronics circuits one being provided for one of the terminal pins of the IC under test
119
.
First of all, before starting the test of an IC, various kinds of data are set from the main controller
111
. After the various kinds of data have been set, the test of the IC is started. When the main controller
111
issues a test start instruction to the pattern generator
112
, the pattern generator
112
starts to generate a pattern. Accordingly, the time point when the pattern generator
112
starts to generate the pattern is the start time point of the test. The pattern generator
112
supplies test pattern data to the waveform formatter
114
in accordance with the test program. On the other hand, the timing generator
113
generates a timing signal (clock pulse) for controlling operating timings of the waveform formatter
114
, the logical comparator
115
, and the like.
The waveform formatter
114
converts the test pattern data supplied from the pattern generator
112
into a test pattern signal having a real waveform. This test pattern signal is applied to the IC under test (generally called “DUT”)
119
via the driver group
116
which voltage-amplifies the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source
121
. It is to be noted here that in case the IC under test
119
is a memory IC or a memory portion of a systematic LSI is tested or the like, the test pattern signal is stored in a predetermined memory cell of the IC under test
119
and the stored content is read out therefrom in a read cycle performed later. On the contrary, in case the IC under test is a logic IC or a logic portion of a systematic LSI is tested or the like, the result of a logical operation of the test pattern signal is read out from the IC under test
119
as a response signal.
A response signal read out from the IC under test
119
is compared with a reference voltage supplied from the comparison reference voltage source
122
in the comparator group
117
which in turn determines whether or not the response signal has a predetermined logical level, that is, whether or not the response signal has a logical H (logical high) voltage or a logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator
115
where the response signal is compared with an expected value pattern signal outputted from the pattern generator
112
so that whether the IC under test
119
has outputted a normal response signal or not can be determined.
In case the IC under test
119
is a memory IC or a memory portion of a systematic LSI is tested or the like, if the response signal does not coincide with the expected value pattern signal, a decision is rendered that a memory cell having an address of the IC under test
119
from which that response signal has been read out is defective (failure), and a failure signal indicating that fact is generated from the logical comparator
115
. Usually, when a failure signal is generated, a failure data (generally logical “1” signal) being applied to a data input terminal of the failure analysis memory
118
is enabled to be written in the memory, and the failure data is stored in an address of the failure analysis memory
118
specified by an address signal supplied to the failure analysis memory
118
at that time. Generally, since an address signal that is the same as the address signal applied to the IC under test
119
is applied to the failure analysis memory
118
, the failure data is stored in an address of the failure analysis memory
118
that is the same as the address of the IC under test
119
.
On the contrary, when the response signal coincides with the expected value pattern signal, a memory cell of the address of the IC under test
119
from which the response signal has
Advantest Corporation
Gallagher & Lathrop
Lathrop, Esq. David N.
Nguyen Vinh P.
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