Method of manufacturing wafer level package

Details Method of manufacturing wafer level package Method of manufacturing wafer level package

2008-04-25

2009-12-15

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C438S113000, C438S612000, C438S613000, C438S617000, C257SE21507, C257SE21508, C257SE21576, C257SE21589, C257SE21705, C257SE23011, C257SE23021, C257SE29069, C257SE25013

Reexamination Certificate

active

07632709

ABSTRACT:
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

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Korean Patent Office Action, mailed Jul. 25, 2008, and issued in corresponding Korean Patent Application No. 10-2007-0099228.

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