Electrical connectors – Having retainer or passageway for fluent material – Liquid retainer
Reexamination Certificate
1999-08-23
2001-04-17
Nelms, David (Department: 2818)
Electrical connectors
Having retainer or passageway for fluent material
Liquid retainer
C438S149000, C438S152000, C438S166000, C438S231000, C438S238000, C438S295000
Reexamination Certificate
active
06217357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a method of manufacturing a two-power supply voltage compatible CMOS semiconductor device in which the number of photolithography steps for forming an LDD, a pocket, and a source/drain region can be reduced as compared with the prior art.
2. Description of the Prior Art
As a CMOS semiconductor device is more and more micropatterned, its gate length decreases. Accordingly, it is indispensable to suppress a decrease in threshold voltage, i.e., a so-called short-channel effect, and a degradation in hot carriers of mainly an n-type MOSFET. For this purpose, the power supply voltage must be decreased.
In the circuit configuration, it is also necessary to form a MOSFET compatible with the previous-generation power supply voltage at the interface with an external circuit.
From the above reasons, in a CMOS semiconductor device, MOSFETs each compatible with two different power supply voltages, i.e., four types of MOSFETs including a low power supply voltage compatible n-type MOSFET, a low power supply voltage compatible p-type MOSFET, a high power supply voltage compatible n-type MOSFET, and a high power supply voltage compatible p-type MOSFET, must be formed separately on the wafer. Items required for the four types of MOSFETs are as follows.
Since a low power supply voltage compatible MOSFET portion is expected to operate at a high speed, a device must have a small gate length and a high drive capability. Accordingly, a structure capable of suppressing the short-channel effect and having a low parasitic resistance for increasing the drive capability is required.
Since a high power supply voltage compatible MOSFET portion is generally used at only the interface with an external circuit, its drive capability does not matter. Accordingly, a MOSFET having a large gate length is generally used, and suppression of the short-channel effect does not generally become an issue. Since the power supply voltage is high, a degradation in reliability such as hot carrier resistance, and suppression of the junction leakage current between the source/drain and the well pose problems.
Even if the low power supply voltage compatible MOSFET and the high power supply voltage compatible MOSFET are formed on the same wafer, they require separate LDD structures and source/drain structures.
More specifically, low power supply voltage compatible n- and p-type MOSFETs preferably have structures each employing both a comparatively heavily doped LDD layer and a pocket layer in order to satisfy both suppression of the short-channel effect and decrease in parasitic resistance. A high power supply voltage compatible n-type MOSFET must have a lightly doped LDD structure in order to improve the hot carrier resistance. A high power supply voltage compatible p-type MOSFET must have a structure that can suppress the leakage current between the source/drain and the well.
A conventional method of manufacturing a CMOS semiconductor device compatible with two different power supply voltages will be described with reference to
FIGS. 1A
to
1
H. As this prior art, a case wherein the low power supply voltage is 1.8 V and the high power supply voltage is 3.3 V will be described. In the description, the gate length of the 1.8 −V compatible MOSFET is 0.18 &mgr;m as the typical example, and the gate length of the 3.3 −V compatible MOSFET is 0.35 &mgr;m as the typical example.
As shown in
FIG. 1A
, isolation regions
2
, n-type well regions
3
, and p-type well regions
4
are formed in a semiconductor substrate
1
. After that, 1.8 −V power supply voltage compatible thin gate oxide films
5
and 3.3 −V power supply voltage compatible thick gate oxide films
6
are formed.
The gate oxide films
5
and
6
having the two different thicknesses are usually formed in the following manner. A gate oxide film having an appropriate thickness is formed once, and only its 1.8 −V power supply voltage portion is wet-etched to remove the gate oxide film. After that, gate oxidation is performed again for a thickness matching the design of the 1.8 −V power supply voltage portion. The 3.3 −V power supply voltage portion is subjected to gate oxidation twice. The thickness of the first gate oxidation is adjusted so that a gate oxide film having a 3.3 −V power supply voltage compatible thickness is formed (not shown). After that, a gate electrode material is deposited, and photolithography and etching are performed to form gate electrodes
7
.
After that, as shown in
FIG. 1B
, a portion of the substrate
1
other than a prospective 1.8 −V power supply voltage compatible n-type MOSFET formation region
11
is masked with resists
12
(first photolithography step), and an n-type impurity, e.g., As
+
13
, is ion-implanted at a comparatively high concentration to form an n-type LDD region
14
. After that, a p-type impurity, e.g., BF
2
+
15
, is obliquely ion-implanted to form a p-type pocket region
16
.
The 1.8 −V power supply voltage compatible n-type MOSFET is a micropatterned portion having a gate length of 0.18 &mgr;m, and it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the n-type LDD region to have a comparatively high As concentration on the order of about 10
19
cm
−3
. The latter is realized by setting the pocket region to have a boron concentration on the order of about 10
18
cm
−3
.
The resists
12
are removed. As shown in
FIG. 1C
, a portion of the substrate
1
other than a prospective 1.8 −V power supply voltage compatible p-type MOSFET formation region
17
is masked with resists
18
(second photolithography step). After that, a p-type impurity, e.g., BF
2
+
19
, is ion-implanted at a comparatively high concentration to form a p-type LDD region
20
. Then, an n-type impurity, e.g., As
+
21
, is obliquely ion-implanted to form an n-type pocket region
22
.
The 1.8 −V power supply voltage compatible p-type MOSFET is a micropatterned portion having a gate length of 0.18 &mgr;m, and it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the p-type LDD region to have a comparatively high boron concentration on the order of about 10
19
cm
−3
. The latter is realized by setting the pocket region to have an As concentration on the order of about 10
18
cm
−3
.
The resists
18
are removed. As shown in
FIG. 1D
, a portion of the substrate
1
other than a prospective 3.3 −V power supply voltage compatible n-type MOSFET formation region
23
is masked with resists
24
(third photolithography step). After that, an n-type impurity, e.g., P
+
25
, is ion-implanted at a comparatively low concentration to form an n-type LDD region
26
.
The 3.3 −V power supply voltage compatible n-type MOSFET is a region having a large gate length of 0.35 &mgr;m, and a short-channel effect does not occur. Accordingly, pocket implantation is not necessary. Since this region has a large gate length, its parasitic resistance does not pose a problem.
Since the power supply voltage is high, the hot carrier must be suppressed. Accordingly, the n-type LDD region
26
must be formed by using broad-profile P
+
25
to a low concentration on the order of about 10
18
cm
−3
.
The resists
24
are removed. As shown in
FIG. 1E
, a portion of the substrate
1
other than a prospective 3.3 −V power supply voltage compatible p-type MOSFET formation region
27
is masked with resists
28
(fourth photolithography step). After that, a p-type impurity, e.g., BF
2
+
29
, is ion-implanted to form a p-type LDD region
30
.
The 3.3 −V power supply voltage compatible p-type MOSFET is a region having a large gate length of 0.35 &mgr;m, and a short-channel effect does not occur. Accordingly, pocket implantation is not necess
Berry Renee R
NEC Corporation
Nelms David
Sughrue Mion Zinn Macpeak & Seas, PLLC
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