Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-06-05
1998-06-16
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438298, 438450, 438526, H01L 2176, H01L 2174
Patent
active
057670005
ABSTRACT:
A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
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Bandyopadhyay Basab
Brennan William S.
Dawson Robert
Fulford Jr. H. Jim
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Fourson George R.
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