Method of manufacturing solid-state electrolytic capacitor

Details Method of manufacturing solid-state electrolytic capacitor Method of manufacturing solid-state electrolytic capacitor

2003-10-08

2004-09-21

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C029S025030

Reexamination Certificate

active

06794260

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of manufacturing solid electrolytic capacitors to be used in various electronic apparatuses.
BACKGROUND ART
A structure of a conventional solid electrolytic capacitor is described hereinafter with reference to its manufacturing steps. (1) Form a dielectric coating on a face of a porous section of a valve metal sheet, using one face in a thickness direction or a core of an intermediate section of the porous valve metal sheet such as aluminum or tantalum as an electrode. (2) Form a collector layer on a surface of the dielectric coating. (3) Form a capacitor element by providing an electrode layer made of metal on the collector layer. (4) Laminate the capacitor elements. (5) Gather together the electrode sections of respective capacitor elements laminated or electrode layers and couple them to an external terminal. (6) Finally, form an outer case such that the external terminal can be exposed.
The foregoing conventional solid electrolytic capacitor can increase its capacitance and reduce its equivalent series resistance (hereinafter referred to as ESR). In fact, this capacitor is mounted to a circuit board via the external terminal similar to other ordinary solid electrolytic capacitors.
The solid electrolytic capacitors, to be surface-mounted on circuit boards like semiconductor components, are obliged to have a slow response to a high frequency because the presence of terminal lengths or wire lengths increases ESR and equivalent series inductance (ESL) in an actual circuit.
In order to overcome the problem discussed above, both of an anode and a cathode are placed on a surface of a solid electrolytic capacitor so that semiconductor components can be directly mounted on the surface, and as a result, ESR and ESL can be lowered. Such a solid electrolytic capacitor discussed above is proposed.
DISCLOSURE OF THE INVENTION
The present invention aims to provide a method of manufacturing the solid electrolytic capacitors that can be directly connected to semiconductor components and have a larger capacitance as well as faster-response to a high frequency. The manufacturing method of the present invention comprises the following steps:
forming through-holes at given places after forming a resist film on a porous face of aluminum foil, one of both the foil faces having been made porous by etching; then
forming insulating films on the remaining face (non-porous face, and hereinafter referred to as a flat face) and on inner walls of the through-holes; then
forming a dielectric coating on the porous section after removing the resist film; and
forming a solid electrolytic layer on the dielectric coating; then forming through-hole electrodes in the through-holes; and
forming a collector layer on the solid electrolytic layer; then forming openings at given places of the insulating film on the flat face; and
forming connecting terminals on exposed faces of the openings and the through-hole electrodes.


REFERENCES:
patent: 6464739 (2002-10-01), Yoshida et al.
patent: 2-137311 (1990-05-01), None

Affiliated with

Also associated with

Rating

Method of manufacturing solid-state electrolytic capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing solid-state electrolytic capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing solid-state electrolytic capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3225927