Method of manufacturing SOI semiconductor element

Fishing – trapping – and vermin destroying

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437 21, 437 41, 437 61, 437 89, 437203, 257347, H01L 2170

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051889730

ABSTRACT:
According to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.

REFERENCES:
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patent: 4685196 (1987-08-01), Lee
patent: 5120666 (1992-06-01), Gobou
Y. Omura et al., "0.1-.mu.m-Gate, Ultrathin-Film CMOS Devices Using SIMOX Substrate with 80-nm-Thick Buried Oxide Layer", CH3075-9/91/0000-0675$1.00 .COPYRGT.1991 IEEE, pp. 675-678.
J. P. Colinge et al., "Silicon-On-Insulator Gate-All-Around Device", CH2865-4/90/0000-0595 $1.00 .COPYRGT.1990 IEEE, pp. 595-598.
Tetsu Tanaka et al., "Analysis of P.sup.+ Poly Si Double-Gate Thin-Film SOI MOSFETS", CH3075-9/91/0000-0683 $1.00 .COPYRGT.1991 IEEE, pp. 683-686.

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