Method of manufacturing shallow trench isolation

Details Method of manufacturing shallow trench isolation Method of manufacturing shallow trench isolation

1999-03-16

2001-03-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S400000

Reexamination Certificate

active

06204147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a shallow trench isolation.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs.
Currently, shallow trench isolation (STI) technique employs a method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate having a pad oxide layer thereon and a silicon nitride layer on the pad oxide layer, and then depositing an oxide layer in the trench and over the substrate. Next, a chemical-mechanical polishing step is used to planarize the oxide layer to expose the surface of the silicon nitride layer. In the subsequent step, a wet etching step is used to remove successively the silicon nitride layer and the pad oxide layer. At this point, the STI process is finished.
As shown in
FIG. 1
, since the etching rate of the STI
24
is faster than that of the silicon nitride layer (not shown), portions of the STI
24
removed by the wet etching are thicker than the silicon nitride layer while the silicon nitride layer is removed by the wet etching to expose the surface of the pad oxide layer. Therefore, the STI
24
has substantially the same surface level as the surface of a substrate
10
.
However, because the etching rate of the STI edge is faster than that of the centric STI, there are many recess defects
26
formed on the surface of the STI
24
along the top edge of the trench
18
while the silicon nitride layer and the pad oxide layer (not shown) are stripped away. The recess defects
26
lead to leakage and short circuit of the devices. Moreover, the reliability and the yield of the devices are reduced.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a method of manufacturing a shallow trench isolation. By using the invention, reliability and yield can be improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer and a trench penetrates through the silicon oxide layer and the pad oxide layer and into the substrate. A first oxide layer is formed on the silicon nitride layer conformally. A rapid thermal process is performed. A second oxide layer is formed on the oxide layer to fill the trench. Portions of the first and the second oxide layers are removed to expose the silicon nitride layer. Since the first oxide layer is shrunk after the rapid thermal process is performed, there is no void in the shallow trench isolation after the second oxide layer fills the trench. Moreover, after the rapid thermal process is performed, the etching rate of the first oxide layer is similar to that of the second oxide layer. Therefore, the shallow trench isolation can be prevented from the recess defects formed on the shallow trench along the top edge of the trench and the problems such as leakage and short circuit, which are caused by the recess defects, can be overcome.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5981353 (1999-11-01), Tsai
patent: 6001704 (1999-12-01), Cheng et al.
patent: 6020251 (2000-02-01), Peng et al.
patent: 6066543 (2000-05-01), Takahashi et al.
patent: 6087243 (2000-07-01), Wang

Affiliated with

Also associated with

Rating

Method of manufacturing shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing shallow trench isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2455066