Method of manufacturing shallow trench isolation

Details Method of manufacturing shallow trench isolation Method of manufacturing shallow trench isolation

1998-12-08

2001-01-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S296000

Reexamination Certificate

active

06177332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, the local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quiet a period of time, it is one of the most reliable and low-cost methods for fabricating device isolation region. However, there are still some drawbacks of the LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by isolation regions is especially difficult to avoid; thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing an oxide layer in the trench and on the substrate. Next, a chemical-mechanical polishing step is used to planarize the oxide layer and to form an STI region. Therefore, the problem induced by the bird's beak can be overcome. As line width becomes smaller and integration becomes higher, STI is an ideal and scaleable isolation technique.
FIGS. 1A through 1D
are schematic, cross-sectional views of the conventional process for manufacturing an STI.
As shown in
FIG. 1A
, a substrate
100
is provided. There are a pad oxide layer
102
and a mask layer
104
on the substrate, and a trench
106
penetrate through the mask layer
104
and the pad oxide layer
102
and into the substrate
100
. A liner oxide layer
108
is conformally formed on the bottom surface and a portion of the sidewall of the trench
106
in the substrate
100
.
As shown in
FIG. 1B
, an insulating layer
110
is formed over the substrate and filling the trench
106
. A densification step is used to increase the density of the insulating layer
110
.
As shown in
FIG. 1C
, a chemical-mechanical polishing (CMP) step is used to planarize the insulating layer
110
until the surface of the mask layer
104
is exposed and to form an STI
112
.
As shown in
FIG. 1D
, the mask layer
104
and the pad oxide layer
102
are removed in sequence.
When the CMP step is performed, since the insulating layer
110
is softer than the mask layer
104
, the surfaces
114
a
and
114
b
of the STI
112
manifest dishing (as shown in FIG.
1
C). Moreover, since the polishing rates are different between the dense region
116
a
and the thin region
116
b
of the STI
112
, the recess of the surface
114
b
in the thin region
116
b
is deeper than that of the surface
114
a
in the dense region
116
a.
Therefore, the nonuniformity of the thickness of the STI affects the subsequent process. Additionally, the slurry reagent used in CMP can react with the wafer, and then the abrasive particles polish the rough surface. Since the abrasive particles scratch the surface to form microscratches, the bridging effect occurs in subsequent process.
To improve the dishing induced by CMP, many methods are developed, such as reverse mask technique and dummy pattern technique. But the methods mentioned above all require an increase in photolithography and etching steps. The process for manufacturing the STI is more complicated and the costs are increased.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a method of manufacturing a shallow trench isolation. The invention can overcome the problems caused by CMP such as the dishing effect and the nonuniform thickness of the STI.
It is another an objective of the invention to provide a method of manufacturing a shallow trench isolation. The invention can overcome the problems of microscratches on the surface of the STI induced by CMP.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a shallow trench isolation comprising the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrate through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a surface level with the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4551910 (1985-11-01), Patterson
patent: 4689656 (1987-08-01), Silvestri et al.
patent: 4758531 (1988-07-01), Beyer et al.
patent: 5236863 (1993-08-01), Iranmanesh
patent: 5384280 (1995-01-01), Aoki et al.
patent: 5716868 (1998-02-01), Nagai
patent: 6020230 (2000-02-01), Wu
patent: 08306797 (1996-11-01), None

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