Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1997-03-25
1999-08-24
Utech, Benjamin
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438692, 438706, H01L 21302
Patent
active
059424451
ABSTRACT:
According to the invention, the flatness and quality can be improved while simplifying the process even when large size wafers of 200 to 300 mm or above are processed. Basic steps involved are a slicing step E for obtaining thin disc-shape wafers by slicing, a chamfering step F for chamfering the sliced wafers, a flattening step G for flattening the chamfered wafers, an alkali etching step H for removing process damage layers from the flattened wafers, and a double-side polishing step K of simultaneously polishing the two sides of the etched wafers. If necessary, a plasma etching step is used in lieu of the flattening and etching steps G and H respectively.
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patent: 5700179 (1997-12-01), Hasegawa et al.
patent: 5800725 (1998-09-01), Kato et al.
Wolf et al., "Silicon Processing for the VLSI Era", vol. 1, pp. 546-547 1986.
J. Haisma et al. (1994) "Improved Geometry of Double-Sided Polished Parallel Wafers Prepared for Direct Wafer Bonding". Applied Optics 33:7945-54.
Patent Abstracts of Japan vol. 4, No. 165, Nov. 15, 1980. Abstract of JP 55-113332.
Kato Tadahiro
Kudo Hideo
Masumura Hisashi
Okuni Sadayuki
Chen Kin-Chan
Shin-Etsu Handotai & Co., Ltd.
Utech Benjamin
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