Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2002-11-22
2004-06-01
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S243000
Reexamination Certificate
active
06743693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory including a memory cell array and a peripheral circuit thereof.
2. Description of the Background Art
FIGS. 26 and 29
to
33
are sectional views showing a background method of manufacturing a semiconductor memory in sequential order. The semiconductor memory includes a region in which a memory cell array is formed (hereinafter referred to as “memory cell array forming region”) and a region in which a peripheral circuit of the memory cell array is formed (hereinafter referred to as “peripheral circuit forming region”). A memory cell array constituting a DRAM, for example, is formed in the memory cell array forming region, and a peripheral circuit including a sense amplifier, a sub-decoder and the like is formed in the peripheral circuit forming region. Referring to
FIGS. 26 and 29
to
33
, the background method of manufacturing the semiconductor memory will be described.
As shown in
FIG. 26
, a plurality of bit lines
103
are formed in the memory cell array forming region, and a bit line
106
is formed in the peripheral circuit forming region adjacent to the memory cell array forming region. Then, an insulation layer
118
is formed in the memory cell array forming region and peripheral circuit forming region to cover the bit lines
103
and
106
. The insulation layer
118
is made of a silicon oxide film, for example.
Next, a plurality of storage node contact plugs (hereinafter referred to as “SC plugs”)
107
are provided in the insulation layer
118
in the memory cell array forming region. The SC plugs
107
have top surfaces exposed from the insulation layer
118
and are arranged in a matrix in the direction perpendicular to the film thickness direction of the insulation layer
118
. The SC plugs
107
are made of doped polysilicon or metal, for example.
The bit lines
103
each have a stacked structure of a conductive film
101
made of doped polysilicon, metal or the like and a silicon nitride film
102
. The bit line
106
also has a stacked structure of a conductive film
104
made of doped polysilicon, metal or the like and a silicon nitride film
105
, similarly to the bit lines
103
.
Although not shown, a semiconductor substrate provided with a plurality of semiconductor elements is present under the insulation layer
118
. A plurality of MOS transistors are formed in a matrix on the semiconductor substrate in the memory cell array forming region while a transistor which constitutes the peripheral circuit is formed in the semiconductor substrate in the peripheral circuit forming region. The SC contact plugs
107
are each provided for each of the MOS transistors formed on the semiconductor substrate and electrically connected to one of source/drain regions of each MOS transistor. The bit lines
103
and
106
are electrically connected to the other source/drain region of each MOS transistor to which no SC plug
107
is connected.
Next, a silicon nitride film
108
and an insulation layer
109
made of, e.g., a silicon oxide film are stacked in this order on the upper surfaces of the insulation layer
118
and the SC plugs
107
. Accordingly, the silicon nitride film
108
and insulation layer
109
are provided in the memory cell array forming region and peripheral circuit forming region. Then, a photoresist (not shown) is formed over the insulation layer
109
and the photoresist is exposed using a photomask (not shown) having a predetermined mask pattern. As a result, the mask pattern of the photomask is transferred to the photoresist. The photoresist is then developed, and a predetermined opening pattern is formed on the photoresist.
Next, the insulation layer
109
and silicon nitride film
108
are etched using the photoresist having the predetermined opening pattern formed thereon as a mask. Accordingly, a plurality of openings
110
for exposing the SC plugs
107
are formed in the insulation layer
109
and silicon nitride film
108
in the memory cell array forming region, and a trench
120
is further formed in the insulation layer
109
and silicon nitride film
108
at the border between the memory cell array forming region and peripheral circuit forming region. The photomask used for forming the openings
110
and the trench
120
will be described later in detail.
Next, a polysilicon film is entirely formed, part of which is present above the openings
110
and the trench
120
is removed by a CMP method. Accordingly, a lower electrode
111
of a capacitor made of a polysilicon film is formed on the surface of each of the openings
110
, and a guard ring film
121
made of a polysilicon film is formed on the surface of the trench
120
.
FIG. 27
is a plan view showing the structure of
FIG. 26
viewed from an arrow C.
FIG. 27
illustrates the SC plugs
107
, bit lines
103
and
106
in broken lines which actually do not appear in the plan view.
FIG. 26
is a sectional view taken along the line D—D of FIG.
27
.
As shown in
FIG. 27
, the openings
110
are each provided for each of the SC plugs
107
and arranged in a matrix in the direction perpendicular to the film thickness direction of the insulation layer
109
. Specifically, the openings
110
are arranged at a pitch P
200
in the column direction and at a pitch P
100
in the row direction.
The trench
120
is formed to surround the openings
110
. Part of the trench
120
extending in the column direction is spaced at a pitch P
101
from the most adjacent ones of the openings
110
aligned in the column direction, while part of the trench
120
extending in the row direction is spaced at a pitch P
201
from the most adjacent ones of the openings
110
aligned in the row direction. The “column direction” and “row direction” denote the left-to-right direction and top-to-bottom direction of the drawing sheet, respectively.
FIG. 28
is a plan view showing a photomask
300
used for forming the openings
110
and the trench
120
shown in FIG.
27
. The photomask
300
is a positive-type photoresist, for example.
As shown in
FIG. 28
, the photomask
300
is provided with a mask pattern
301
including a plurality of patterns
200
corresponding to the openings
110
and a pattern
201
corresponding to the trench
120
. The patterns
200
are arranged in a matrix at a pitch P
210
in the column direction and at a pitch P
110
in the row direction.
The pattern
201
is formed to surround the patterns
200
. Part of the pattern
201
extending in the column direction is spaced at a pitch P
111
from the most adjacent ones of the patterns
200
aligned in the column direction, while part of the pattern
201
extending in the row direction is spaced at a pitch P
211
from the most adjacent ones of the patterns
200
aligned in the row direction.
In the case where the mask pattern
301
is transferred to the photoresist on an equal scale, the pitches P
110
, P
111
, P
210
and P
211
correspond to the pitches P
100
, P
101
, P
200
and P
201
shown in
FIG. 27
, respectively. In the case where the mask pattern
301
is transferred to the photoresist on a reduced scale, e.g., on a one-fifth scale, the pitches P
110
, P
111
, P
210
and P
211
are five times the pitches P
100
, P
101
, P
200
and P
201
shown in
FIG. 27
, respectively.
Next, as shown in
FIG. 29
, a resist
130
is formed on the insulation layer
109
and guard ring film
121
in the peripheral circuit forming region. Accordingly, the trench
120
is filled with the resist
130
. Then, as shown in
FIG. 30
, the insulation layer
109
is selectively etched using the resist
130
as a mask to remove the insulation layer
109
in the memory cell array forming region. As shown in
FIG. 31
, the resist
130
is then removed.
Next, as shown in
FIG. 32
, a dielectric film
112
of a capacitor is formed on the lower electrode
111
, guard ring film
121
and silicon nitride film
108
in the memory cell array forming region, and an upper electrode
113
of the capacitor is formed on the dielectric
Nhu David
Renesas Technology Corp.
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